Intel SL3QA - Pentium III 550 MHz Processor Specification page 74

will not be loaded. This will lead to the reporting of invalid TSS fault instead of the
expected Double fault
Implication: Operating systems that access an invalid TSS may get invalid TSS fault instead of a
Double fault.
Workaround: Software needs to ensure any accessed TSS is valid.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E73. Machine
Between Different Memory Types
Problem: A small window of opportunity exists where code fetches interleaved between
different memory types may cause a machine check exception.
micro-architectural boundary conditions is required to expose this window.
Implication: Interleaved instruction fetches between different memory types may result in a
machine check exception.
disabled.
commercially available applications or operating systems.
Workaround: Software can avoid this erratum by placing a serializing instruction between code
fetches between different memory types.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section
E74. Wrong ESP Register Values During a Fault in VM86 Mode
Problem: At the beginning of the IRET instruction execution in VM86 mode, the lower 16 bits of
the ESP register are saved as the old stack value. When a fault occurs, these 16 bits
are moved into the 32-bit ESP, effectively clearing the upper 16 bits of the ESP.
Implication: This erratum has not been observed to cause any problems with commercially
available software.
Workaround: None identified
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E75. APIC ICR Write May Cause Interrupt Not to be Sent When ICR
Delivery Bit Pending
Problem: If the APIC ICR (Interrupt Control Register) is written with a new interrupt command
while the Delivery Status bit from a previous interrupt command is set to '1' (Send
Pending), the interrupt message may not be sent out by the processor.
Implication: This erratum will cause an interrupt message not to be sent, potentially resulting in
system hang.
74
Check Exception
The system may hang if machine check exceptions are
Intel has not observed the occurrence of this erratum while running
May Occur When Interleaving Code
Errata
A complex set of
Specification Update