Intel SL3QA - Pentium III 550 MHz Processor Specification page 69

Errata
3. Avoid using a sub or xor to zero a partial register prior to the use of any of these
three instructions. Instead, use a mov immediate (e.g. "mov ah, 0h").
*Note: MOV EAX, EAX is used here in a generic sense. Again, EAX can be substituted
with any 32-bit register.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E60. FLUSH# Assertion Following STPCLK# May Prevent CPU Clocks From
Stopping
Problem: If FLUSH# is asserted after STPCLK# is asserted, the cache flush operation will not
occur until after STPCLK# is de-asserted.
prevent the processor from entering the Sleep state, since the flush operation must
complete prior to the processor entering the Sleep state.
Implication: Following SLP# assertion, processor power dissipation may be higher than expected.
Furthermore, if the source to the processor's input bus clock (BCLK) is removed,
normally resulting in a transition to the Deep Sleep state, the processor may
shutdown improperly. The ensuing attempt to wake up the processor will result in
unpredictable behavior and may cause the system to hang.
Workaround: For systems that use the FLUSH# input signal and Deep Sleep state of the
processor, ensure that FLUSH# is not asserted while STPCLK# is asserted.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E61. Intermittent Failure to Assert ADS# During Processor Power-On
Problem: Under a system specific set of initial parametric conditions, a very small number of
Pentium® III processors (CPUID 068xh) may be susceptible to entering an internal
test mode during processor power-on.
assert ADS# during a processor power-on.
Implication: On susceptible platforms, when power is applied to the processor, there is a
possibility that the processor will occasionally enter the test mode rather than initiate
a system boot sequence.
A subsequent processor Power-Off then Power-On cycle should remove the processor
from this test mode, allowing normal processor operation to resume. The following
workaround also may reduce the occurrence of the failure condition:
Specification Update
MOVSX AX, BL (or other MOVSX, other IMUL or CBW instruction)
*MOV EAX, EAX
MOVD MM0, EAX or CVTSI2SS MM0, EAX
Furthermore, the pending flush will
The symptom of this test mode is a failure to
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