Intel SL3QA - Pentium III 550 MHz Processor Specification page 60

Problem: If a processor is underclocked at a core frequency to system bus frequency ratio of
2:1 and system bus ECC is enabled, the system bus ECC detection and correction will
negatively affect internal timing dependencies.
Implication: If system bus ECC is enabled, and the processor is underclocked at a 2:1 ratio, the
system may behave unpredictably due to these timing dependencies.
Workaround: All bus agents that support system bus ECC must disable it when a 2:1 ratio is
used.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E42. Processor May Assert DRDY# on a Write With No Data
Problem: When a MASKMOVQ instruction is misaligned across a chunk boundary in a way that
one chunk has a mask of all 0's, the processor will initiate two partial write
transactions with one having all byte enables deasserted. Under these conditions, the
expected behavior of the processor would be to perform both write transactions, but
to deassert DRDY# during the transaction which has no byte enables asserted. As a
result of this erratum, DRDY# is asserted even though no data is being transferred.
Implication: The implications of this erratum depend on the bus agent's ability to handle this
erroneous DRDY# assertion. If a bus agent cannot handle a DRDY# assertion in this
situation, or attempts to use the invalid data on the bus during this transaction,
unpredictable system behavior could result
Workaround: A system which can accept a DRDY# assertion during a write with no data will not
be affected by this erratum. In addition, this erratum will not occur if the MASKMOVQ
is aligned.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E43. GP# Fault on WRMSR to ROB_CR_BKUPTMPDR6
Problem: Writing a '1' to unimplemented bit(s) in the ROB_CR_BKUPTMPDR6 MSR (offset 1E0h)
will result in a general protection fault (GP#).
Implication: The normal process used to write an MSR is to read the MSR using RDMSR, modify
the bit(s) of interest, and then to write the MSR using WRMSR. Because of this
erratum, this process may result in a GP# fault when used to modify the
ROB_CR_BKUPTMPDR6 MSR.
Workaround: When writing to ROB_CR_BKUPTMPDR6 all unimplemented bits must be '0.'
Implemented bits may be set as '0' or '1' as desired.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E44. Machine Check Exception May Occur Due to Improper Line Eviction in
the IFU
60
Errata
Specification Update