Thread And Core C-State Entry And Exit; Coordination Of Thread Power States At The Core Level - Intel BX80605X3430 - Xeon 2.4 GHz Processor Datasheet

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Entry and exit of the C-States at the thread and core level are shown in

Figure 4-2.

Thread and Core C-State Entry and Exit

While individual threads can request low power C-states, power saving actions only

take place once the core C-state is resolved. Core C-states are automatically resolved

by the processor. For thread and core C-states, a transition to and from C0 is required

before entering any other C-state.

Table 4-3.

Processor Core

C-State

Thread 0

Note:

If enabled, the core C-state will be C1E if all active cores have also resolved to a core C1 state or higher.

MWAIT(C 1), HLT

MWAIT(C1), HLT

(C1E Enabled)

C1E

MWAIT(C6),

P_LVL3 I/O Read

MWAIT(C3),

P_LVL2 I/O Read

C 3

Thread 1

Power Management

Figure

4-2.

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