Memory Channel B - Intel BX80605X3430 - Xeon 2.4 GHz Processor Datasheet

Signal Description
Table 6-3.

Memory Channel B

Signal Name
SB_BS[2:0]
SB_CAS#
SB_CK#[1:0]
SB_CK#[3:2]
SB_CK[1:0]
SB_CK[3:2]
SB_CKE[3:0]
SB_CS#[3:0]
SB_CS#[7:4]
SB_DM[7:0]
SB_DQ[63:0]
SB_DQS[8:0]
SB_DQS#[8:0]
SB_ECC_CB[7:0]
SB_MA[15:0]
SB_ODT[3:0]
SB_RAS#
SB_WE#
Datasheet, Volume 1
Description
Bank Select: These signals define which banks are
selected within each SDRAM rank.
CAS Control Signal: This signal is used with SB_RAS#
and SB_WE# (along with SB_CS#) to define the SDRAM
Commands.
SDRAM Inverted Differential Clock: Channel B SDRAM
Differential clock signal-pair complement.
SDRAM Inverted Differential Clock: Channel B SDRAM
Differential clock signal-pair complement.
SDRAM Differential Clock: Channel B SDRAM Differential
clock signal pair.
The crossing of the positive edge of SB_CKx and the
negative edge of its complement SB_CKx# are used to
sample the command and control signals on the SDRAM.
SDRAM Differential Clock: Channel B SDRAM Differential
clock signal pair.
The crossing of the positive edge of SB_CKx and the
negative edge of its complement SB_CKx# are used to
sample the command and control signals on the SDRAM.
Clock Enable: (1 per rank). These signals are used to:
• Initialize the SDRAMs during power-up
• Power-down SDRAM ranks
• Place all SDRAM ranks into and out of self-refresh
during STR
Chip Select: (1 per rank) These signals are used to select
particular SDRAM components during the active state.
There is one Chip Select for each SDRAM rank.
These signals are only used for processors and platforms
that have Registered DIMM support. These signals are
used to select particular SDRAM components during the
active state and SB_CS#[7:6] are used as the on die
termination for the first DIMM.
Data Mask: These signals are used to mask individual
bytes of data in the case of a partial write, and to
interrupt burst writes. When activated during writes, the
corresponding data groups in the SDRAM are masked.
There is one SB_DM[7:0] for every data byte lane.
Note: These signals are not used by the Intel Xeon
processor 3400 series. They are connected to V
package.
Data Bus: Channel B data signal interface to the SDRAM
data bus.
Data Strobes: SB_DQS[8:0] and its complement signal
group make up a differential strobe pair. The data is
captured at the crossing point of SB_DQS[8:0] and its
SB_DQS#[8:0] during read and write transactions.
Data Lines for ECC Check Byte.
Memory Address: These signals are used to provide the
multiplexed row and column address to the SDRAM.
On-Die Termination: Active Termination Control.
RAS Control Signal: This signal is used with SB_CAS#
and SB_WE# (along with SB_CS#) to define the SDRAM
Commands.
Write Enable Control Signal: This signal is used with
SB_RAS# and SB_CAS# (along with SB_CS#) to define
the SDRAM Commands.
Direction
O
O
O
O
O
O
O
O
O
on the
SS
I/O
I/O
I/O
O
O
O
O
Type
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
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