Peripheral Circuits And Their Operation; I/O Memory Map - Epson S1C88650 Technical Manual

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
5 PERIPHERAL CIRCUITS AND
THEIR OPERATION
The peripheral circuits of the S1C88650 is interfaced with the CPU by means of the memory mapped
I/O method. For this reason, just as with other memory access operations, peripheral circuits can be
controlled by manipulating I/O memory. Below is a description of the operation and control method for
each individual peripheral circuit.

5.1 I/O Memory Map

Address Bit Name
00FF00 D7 BUSMOD
Bus mode
(MCU) D6 CPUMOD CPU mode
D5 –
R/W register
D4 – R/W register
D3 –
R/W register
D2 CE2 CE2 (R32)
D1 CE1 CE1 (R31)
D0 CE0
CE0 (R30)
00FF00 D7 BUSMOD Bus mode
(MPU) D6 CPUMOD
CPU mode
D5 – R/W register
D4 –
R/W register
D3 – R/W register
D2 CE2
CE2 (R32)
D1 CE1 CE1 (R31)
D0 CE0 CE0 (R30)
00FF01 D7 SPP7
Stack pointer page address
D6 SPP6
D5 SPP5
< SP page allocatable address >
D4 SPP4 • Single chip mode:
D3 SPP3
• Expansion mode:
D2 SPP2
D1 SPP1
D0 SPP0
00FF02 D7 EBR Bus release enable register
(K03 and R33 terminal specification)
D6 WT2 Wait control register
D5 WT1
D4 WT0
D3 CLKCHG CPU operating clock switch
D2 SOSC3
OSC3 oscillation On/Off control
D1 – R/W register
D0 –
R/W register
00FF03 D7 – –
D6 – –
D5 –
–
D4 – –
D3 –
–
D2 – –
D1 VDSEL
Power source select for LCD voltage regulator
D0 DBON Power voltage booster On/Off control
Note: All the interrupts including NMI are disabled, until you write the optional value into both the "00FF00H" and
"00FF01H" addresses.
18
Table 5.1.1(a) I/O Memory map (00FF00H–00FF03H)
Function
CE signal output Enable/Disable
Enable: CE signal output
Disable: DC (R3x) output
CE signal output Enable/Disable
Enable: CE signal output
Disable: DC (R3x) output
only 0 page
0–27H page
WT2 WT1 WT0
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
____
1
Expansion Single chip
Maximum Minimum
1
1
1
CE2 enable CE2 disable
CE1 enable CE1 disable
CE0 enable CE0 disable
Expansion
Maximum Minimum
1
1
1
CE2 enable CE2 disable
CE1 enable CE1 disable
CE0 enable CE0 disable
(MSB)
1
1
1
1
1
1
1
(LSB)
1
K03
BREQ Input port
R33
BACK Output port
Number
of state
14
12
10
8
6
4
2
No wait
OSC3
On
1
1
–
–
–
–
–
–
V
D2
On
EPSON
0 SR R/W Comment
0 R/W
0 R/W
0 R/W
0 Reserved register
0 R/W
0
0 R/W
0
0 R/W
In Single chip mode,
0 R/W
these setting are fixed
0 R/W
at DC output.
1 R
– Expansion mode only
0 R/W
0 R/W
0 Reserved register
0 R/W
0
0 R/W
0
0 R/W
0 R/W
1 R/W
0 R/W
0
0 R/W
0
0 R/W
0
0 R/W
0
0 R/W
0
0 R/W
0
0 R/W
0
0 R/W
0
0 R/W
0 R/W
0 R/W
0 R/W
1 R/W
OSC1
1 R/W
Off
0 R/W
0 Reserved register
0 R/W
0
–
– Constantly "0" when
–
– being read
–
–
–
–
–
–
–
–
0 R/W
V
DD
0 R/W
Off
S1C88650 TECHNICAL MANUAL