Epson S1C88650 Technical Manual page 27

Hewlett-packard cmos 8-bit single chip microcomputer technical manual
Table of Contents

Advertisement

Address Bit
Name
00FF10 D7
HLMOD
Heavy load protection mode
D6
SEGREV
Reverse SEG assignment
D5
R/W register
D4
R/W register
D3
R/W register
D2
DTFNT
LCD dot font selection
D1
LDUTY1
LCD drive duty selection
D0
LDUTY0
00FF11 D7
FRMCS
LCD frame signal source clock selection
D6
DSPAR
LCD display memory area selection
D5
LCDC1
LCD display control
D4
LCDC0
D3
LC3
LCD contrast adjustment
D2
LC2
D1
LC1
D0
LC0
00FF12 D7
D6
D5
SVDDT
SVD detection data
D4
SVDON
SVD circuit On/Off
SVD criteria voltage setting
D3
SVDS3
D2
SVDS2
D1
SVDS1
D0
SVDS0
00FF14 D7
PRPRT1
D6
PST12
D5
PST11
D4
PST10
D3
PRPRT0
D2
PST02
D1
PST01
D0
PST00
S1C88650 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(b) I/O Memory map (00FF10H–00FF14H)
Function
LDUTY1
LDUTY0
1
1
Not allowed
1
0
0
1
0
0
LCD display
LCDC1
LCDC0
1
1
All LCDs lit
1
0
All LCDs out
0
1
Normal display
0
0
Drive off
LC3
LC2
LC1
LC0
1
1
1
1
1
1
1
0
:
:
:
:
0
0
0
0
SVDS3
SVDS2
SVDS1
SVDS0
1
1
1
1
1
1
1
1
0
:
:
:
0
0
1
Programmable timer 1 clock control
Programmable timer 1 division ratio
PST12
PST11
PST10
(OSC3)
1
1
1
f
/ 4096
OSC3
1
1
0
f
/ 1024
OSC3
1
0
1
f
/ 256
OSC3
1
0
0
f
/ 64
OSC3
0
1
1
f
/ 32
OSC3
0
1
0
f
/ 8
OSC3
0
0
1
f
/ 2
OSC3
0
0
0
f
/ 1
OSC3
Programmable timer 0 clock control
Programmable timer 0 division ratio
PST02
PST01
PST00
(OSC3)
1
1
1
f
/ 4096
OSC3
1
1
0
f
/ 1024
OSC3
1
0
1
f
/ 256
OSC3
1
0
0
f
/ 64
OSC3
0
1
1
f
/ 32
OSC3
0
1
0
f
/ 8
OSC3
0
0
1
f
/ 2
OSC3
0
0
0
f
/ 1
OSC3
1
On
Reverse
1
1
1
12 12
Duty
1/16
1/32
1/8
PTM
Display area 1 Display area 0
Contrast
Dark
:
:
Light
Low
On
Voltage (V)
1
2.7
0
2.6
1
2.5
:
:
1
1.8
On
(OSC1)
f
/ 128
OSC1
f
/ 64
OSC1
f
/ 32
OSC1
f
/ 16
OSC1
f
/ 8
OSC1
f
/ 4
OSC1
f
/ 2
OSC1
f
/ 1
OSC1
On
(OSC1)
f
/ 128
OSC1
f
/ 64
OSC1
f
/ 32
OSC1
f
/ 16
OSC1
f
/ 8
OSC1
f
/ 4
OSC1
f
/ 2
OSC1
f
/ 1
OSC1
EPSON
0
SR R/W
Comment
0
R/W
Off
0
R/W
Normal
0
R/W
0
Reserved register
0
R/W
0
0
R/W
0
0
R/W
16 16/5 8
1
R/W
0
R/W
0
R/W
f
OSC1
0
R/W
These bits are reset
0
R/W
to (0, 0) when
SLP instruction
is executed.
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Constantly "0" when
being read
0
R
Normal
0
R/W
Off
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Off
0
R/W
0
R/W
0
R/W
0
R/W
Off
0
R/W
0
R/W
0
R/W
19

Advertisement

Table of Contents
loading

Table of Contents