Epson S1C88650 Technical Manual page 39

Hewlett-packard cmos 8-bit single chip microcomputer technical manual
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Address Bit
Name
00FFB0
D7
MODE16_C
PTM4–5 8/16-bit mode selection
D6
PTNREN_C
External clock 2 noise rejecter selection
D5
D4
R/W register
D3
R/W register
D2
PTRUN4
PTM4 Run/Stop control
D1
PSET4
PTM4 preset
D0
CKSEL4
PTM4 input clock selection
00FFB1 D7
D6
D5
D4
R/W register
D3
R/W register
D2
PTRUN5
PTM5 Run/Stop control
D1
PSET5
PTM5 preset
D0
CKSEL5
PTM5 input clock selection
00FFB2
D7
RDR47
PTM4 reload data D7 (MSB)
D6
RDR46
PTM4 reload data D6
D5
RDR45
PTM4 reload data D5
D4
RDR44
PTM4 reload data D4
D3
RDR43
PTM4 reload data D3
D2
RDR42
PTM4 reload data D2
D1
RDR41
PTM4 reload data D1
D0
RDR40
PTM4 reload data D0 (LSB)
00FFB3
D7
RDR57
PTM5 reload data D7 (MSB)
D6
RDR56
PTM5 reload data D6
D5
RDR55
PTM5 reload data D5
D4
RDR54
PTM5 reload data D4
D3
RDR53
PTM5 reload data D3
D2
RDR52
PTM5 reload data D2
D1
RDR51
PTM5 reload data D1
D0
RDR50
PTM5 reload data D0 (LSB)
00FFB4
D7
CDR47
PTM4 compare data D7 (MSB)
D6
CDR46
PTM4 compare data D6
D5
CDR45
PTM4 compare data D5
D4
CDR44
PTM4 compare data D4
D3
CDR43
PTM4 compare data D3
D2
CDR42
PTM4 compare data D2
D1
CDR41
PTM4 compare data D1
D0
CDR40
PTM4 compare data D0 (LSB)
00FFB5
D7
CDR57
PTM5 compare data D7 (MSB)
D6
CDR56
PTM5 compare data D6
D5
CDR55
PTM5 compare data D5
D4
CDR54
PTM5 compare data D4
D3
CDR53
PTM5 compare data D3
D2
CDR52
PTM5 compare data D2
D1
CDR51
PTM5 compare data D1
D0
CDR50
PTM5 compare data D0 (LSB)
S1C88650 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (I/O Memory Map)
Table 5.1.1(n) I/O Memory map (00FFB0H–00FFB5H)
Function
EPSON
1
0
SR R/W
-
-
0
16
bit x 1
8
bit x 2
0
Enable
Disable
0
1
0
0
1
0
0
Run
Stop
0
Preset
No operation
0
External clock
Internal clock
0
1
0
0
1
0
0
Run
Stop
0
Preset
No operation
0
External clock
Internal clock
1
High
Low
1
High
Low
0
High
Low
0
High
Low
Comment
R/W
R/W
"0" when being read
R/W
Reserved register
R/W
R/W
W
"0" when being read
R/W
Constantly "0" when
being read
R/W
Reserved register
R/W
R/W
W
"0" when being read
R/W
R/W
R/W
R/W
R/W
31

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