Epson S1C88650 Technical Manual page 114

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
ETU0: 00FF25H•D0
ETU1: 00FF25H•D2
ETU2: 00FF25H•D4
ETU3: 00FF25H•D6
ETU4: 00FF2CH•D0
ETU5: 00FF2CH•D2
ETU6: 00FF2CH•D4
ETU7: 00FF2CH•D6
Enables or disables the underflow interrupt
generation to the CPU.
When "1" is written: Interrupt is enabled
When "0" is written: Interrupt is disabled
Reading:
The ETUx register is the interrupt enable register
corresponding to the underflow interrupt factor of
Timer x.
Interrupt in which the ETUx register is set to "1" is
enabled, and the others in which the ETUx register
is set to "0" are disabled.
In the 16-bit mode, the setting of the ETU(L) is
invalid.
At initial reset, this register is set to "0" (interrupt
is disabled).
ETC0: 00FF25H•D1
ETC1: 00FF25H•D3
ETC2: 00FF25H•D5
ETC3: 00FF25H•D7
ETC4: 00FF2CH•D1
ETC5: 00FF2CH•D3
ETC6: 00FF2CH•D5
ETC7: 00FF2CH•D7
Enables or disables the compare match interrupt
generation to the CPU.
When "1" is written: Interrupt is enabled
When "0" is written: Interrupt is disabled
Reading:
The ETCx register is the interrupt enable register
corresponding to the compare match interrupt
factor of Timer x.
Interrupt in which the ETCx register is set to "1" is
enabled, and the others in which the ETCx register
is set to "0" are disabled.
In the 16-bit mode, the setting of the ETC(L) is
invalid.
At initial reset, this register is set to "0" (interrupt
is disabled).
106
Valid
Valid
FTU0: 00FF29H•D0
FTU1: 00FF29H•D2
FTU2: 00FF29H•D4
FTU3: 00FF29H•D6
FTU4: 00FF2EH•D0
FTU5: 00FF2EH•D2
FTU6: 00FF2EH•D4
FTU7: 00FF2EH•D6
Indicates the generation of underflow interrupt
factor.
When "1" is read:
When "0" is read:
When "1" is written: Factor flag is reset
When "0" is written: Invalid
FTUx is the interrupt factor flag corresponding to
interrupt of Timer x, and is set to "1" due to the
counter underflow.
At this point, if the corresponding interrupt enable
register is set to "1" and the corresponding inter-
rupt priority register is set to a higher level than
the setting of the interrupt flags (I0 and I1), an
interrupt is generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag is set to "1" when the interrupt genera-
tion condition is met.
To accept the subsequent interrupt after an
interrupt generation, it is necessary to re-set the
interrupt flags (set the interrupt flag to a lower
level than the level indicated by the interrupt
priority registers, or execute the RETE instruction)
and to reset the interrupt factor flag. The interrupt
factor flag is reset to "0" by writing "1".
In the 16-bit mode, the interrupt factor flag FTU(L)
is not set to "1" and Timer(L) interrupt is not
generated. In this mode, the interrupt factor flag
FTU(H) is set to "1" by the underflow of the 16-bit
counter.
At initial reset, this flag is reset to "0".
FTC0: 00FF29H•D1
FTC1: 00FF29H•D3
FTC2: 00FF29H•D5
FTC3: 00FF29H•D7
FTC4: 00FF2EH•D1
FTC5: 00FF2EH•D3
FTC6: 00FF2EH•D5
FTC7: 00FF2EH•D7
Indicates the generation of compare match inter-
rupt factor.
When "1" is read:
When "0" is read:
When "1" is written: Factor flag is reset
When "0" is written: Invalid
EPSON
Int. factor has generated
Int. factor has not generated
Int. factor has generated
Int. factor has not generated
S1C88650 TECHNICAL MANUAL