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1 INTRODUCTION
1.3.2 Pin description
Pin name
Pin No.
V
131, 189
DD
V
67, 134, 195, 253
SS
V
D1
V
D2
V
V
125–121
C1–
C5
CA–CG
120–114
OSC1
OSC2
OSC3
OSC4
MCU/MPU
K00–K02
148–146
K03/BREQ
K04/EXCL0
K05/EXCL1
K06/EXCL2
K07/EXCL3
R00–R07/A0–A7
165–172
R10–R17/A8–A15
173–180
R20–R23/A16–A19
181–184
R24/RD
R25/WR
R30–R32/CE0–CE2
187, 188, 196
R33 (BACK)
P00–P07/D0–D7
164–157
P10/SIN
P11/SOUT
P12/SCLK
P13/SRDY
P14/TOUT0/TOUT1
P15/TOUT2/TOUT3
P16/FOUT
P17/TOUT2/TOUT3
COM0–COM31
198–213, 112–97
SEG0–SEG125
214–252, 4–61,
68–96
RESET
TEST
TEST
4
Table 1.3.2.1 S1C88650 pin description
In/Out
–
Power supply (+) terminal
–
Power supply (GND) terminal
135
–
Internal logic system and oscillation system voltage regulator output terminals
113
–
LCD circuit power voltage booster output terminal
–
LCD drive voltage output terminals
–
LCD and power voltage booster capacitor connection terminals
136
I
OSC1 oscillation input terminal (select crystal/CR oscillation by mask option)
137
O
OSC1 oscillation output terminal
132
I
OSC3 oscillation input terminal (select crystal/ceramic/CR oscillation by mask option)
133
O
OSC3 oscillation output terminal
140
I
MCU/MPU mode setup terminal
I
Input terminals (K00–K02)
145
I
Input terminal (K03) or bus request signal input terminal (BREQ)
144
I
Input terminal (K04) or programmable timer external clock input terminal (EXCL0)
143
I
Input terminal (K05) or programmable timer external clock input terminal (EXCL1)
142
I
Input terminal (K06) or programmable timer external clock input terminal (EXCL2)
141
I
Input terminal (K07) or programmable timer external clock input terminal (EXCL3)
O
Output terminals (R00–R07) or address bus (A0–A7)
O
Output terminals (R10–R17) or address bus (A8–A15)
O
Output terminals (R20–R23) or address bus (A16–A19)
185
O
Output terminal (R24) or read signal output terminal (RD)
186
O
Output terminal (R25) or write signal output terminal (WR)
O
Output terminals (R30–R32) or chip enable signal output terminals (CE0–CE2)
197
O
Output terminal (R33) or bus acknowledge signal output terminal (BACK)
I/O
I/O terminals (P00–P07) or data bus (D0–D7)
156
I/O
I/O terminal (P10) or serial I/F data input terminal (SIN)
155
I/O
I/O terminal (P11) or serial I/F data output terminal (SOUT)
154
I/O
I/O terminal (P12) or serial I/F clock I/O terminal (SCLK)
153
I/O
I/O terminal (P13) or serial I/F ready signal output terminal (SRDY)
152
I/O
I/O terminal (P14)
or programmable timer underflow signal output terminal (TOUT0/TOUT1)
151
I/O
I/O terminal (P15)
or programmable timer underflow signal output terminal (TOUT2/TOUT3)
150
I/O
I/O terminal (P16) or clock output terminal (FOUT)
149
I/O
I/O terminal (P17)
or programmable timer underflow inverted signal output terminal (TOUT2/TOUT3)
O
LCD common output terminals
O
LCD segment output terminals
139
I
Initial reset input terminal
138
I
Test input terminal
3
–
Test terminal (open during normal operation)
Function
EPSON
S1C88650 TECHNICAL MANUAL
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