Epson S1C88650 Technical Manual page 54

5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports)
Table 5.5.4.1 Setting the input level check time
CTK02x CTK01x CTK00x Check time ( )
1
1
1
1
0
0
0
0
When OSC1 = 32 kHz, OSC3 = 2 MHz
Check time setup register
CTK00L–CTK02L
K00
Input port Chattering-eliminate
K00D
Input comparison
register KCP00
Address
K01
K02
K03
Check time setup register
CTK00H–CTK02H
K04
Input port Chattering-eliminate
K04D
Input comparison
register KCP04
Address
K05
K06
K07
46
4/f (2 s)
OSC3
2/f (1 s)
OSC3
1/f (0.5 s)
OSC3
4096/f (128 ms)
OSC1
2048/f (64 ms)
OSC1
512/f (16 ms)
OSC1
128/f (4 ms)
OSC1
None –
Address
circuit
Interrupt factor
Interrupt enable
register EK00
Address
circuit
Interrupt factor
Interrupt enable
register EK04
Fig. 5.5.4.1 Configuration of input interrupt circuit
Notes: • Be sure to disable interrupts before
changing the contents of the CTK0x
register. Unnecessary interrupts may
occur if the register is changed when the
corresponding input port interrupts have
been enabled by the interrupt enable
register EK0x.
• The chattering-eliminate check time
means the maximum pulse width that can
be eliminated. The valid interrupt input
needs a pulse width of the set check time
(minimum) to twice that of the check time
(maximum).
• The internal signal may oscillate if the rise /
fall time of the input signal is too long
because the input signal level transition to
the threshold level duration of time is too
long. This causes the input interrupt to
malfunction, therefore setup the input signal
so that the rise/fall time is 25 nsec or less.
flag FK00
Address
Address
flag FK04
Address
Address
EPSON
f OSC1
OSC1
Divider
oscillation circuit
f OSC3
OSC3
Divider
oscillation circuit
Interrupt
priority level
Interrupt
judgement
request
circuit
Interrupt
priority
register
PK00, PK01
Address
S1C88650 TECHNICAL MANUAL