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8 ELECTRICAL CHARACTERISTICS
Serial interface
• Clock synchronous master mode
Condition: V
= 1.8 to 3.6 V, V
DD
Item
Transmitting data output delay time
Receiving data input set-up time
Receiving data input hold time
• Clock synchronous slave mode
Condition: V
= 1.8 to 3.6 V, V
DD
Item
Transmitting data output delay time
Receiving data input set-up time
Receiving data input hold time
• Asynchronous system
Condition: V
= 1.8 to 3.6 V, V
DD
Item
Start bit detection error time
Erroneous start bit detection range time
Note) 1
Start bit detection error time is a logical delay time from inputting the start bit until internal sampling begins operating.
(Time as far as AC is excluded.)
2
Erroneous start bit detection range time is a logical range to detect whether a LOW level (start bit) has been input again
after a start bit has been detected and the internal sampling clock has started.
When a HIGH level is detected, the start bit detection circuit is reset and goes into a wait status until the next start bit.
(Time as far as AC is excluded.)
SCLK OUT
SOUT
SIN
SCLK IN
SOUT
SIN
SIN
Sampling
clock
Erroneous
start bit
detection signal
146
= 0 V, Ta = 25 C, V
= 0.8V
SS
IH1
Symbol
t
smd
t
sms
t
smh
= 0 V, Ta = 25 C, V
= 0.8V
SS
IH1
Symbol
t
ssd
t
sss
t
ssh
= 0 V, Ta = 25 C
SS
Symbol
t
sa
1
t
sa
2
V
OH
V
OL
t
smd
V
OH
V
OL
t
sms
V
IH1
V
IL1
V
IH1
V
IL1
t
ssd
V
OH
V
OL
t
sss
V
IH1
V
IL1
Start bit
t
sa
1
t
sa
2
EPSON
, V
= 0.2V
, V
= 0.8V
DD
IL1
DD
OH
Min.
Typ.
250
100
, V
= 0.2V
, V
= 0.8V
DD
IL1
DD
OH
Min.
Typ.
100
100
Min.
Typ.
0
t
9
/16
t
smh
t
ssh
t
, V
= 0.2V
DD
OL
DD
Max.
Unit
100
ns
ns
ns
, V
= 0.2V
DD
OL
DD
Max.
Unit
250
ns
ns
ns
Max.
Unit
t
/16
s
t
10
/16
s
Stop bit
S1C88650 TECHNICAL MANUAL
Note
Note
Note
1
2
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