Intel MFSYS25V2 Specification page 21

Functional Architecture
achieved across channels. Active channels hold the primary image and the other channels hold
the secondary image of the system memory. The integrated memory controller in the Intel
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Xeon Processor 5500 series and Intel
between both channels for read transactions. Write transactions are issued to both channels
under normal circumstances.
When the system is in the Channel Mirroring mode, channel C and channel F of socket 1 and
socket 2 respectively are not used. Hence, the DIMMs populated on these channels are
disabled and therefore do not contribute to the available physical memory. For example, if the
system is operating in the Channel Mirroring mode and the total size of the DDR3 DIMMs is 1.5
GB (3 x 512 MB DIMMs), and then the active memory is only 1 GB.
Because the available system memory is divided into a primary image and a copy of the image,
the effective system memory is reduced by at least one-half. For example, if the system is
operating in the Channel Mirroring mode and the total size of the DDR3 DIMMs is 1 GB, then
the effective size of the memory is 512 MB because half of the DDR3 DIMMs are the
secondary images.
For channel mirroring to work, participant DDR3 DIMMs on the same DIMM slots on the
adjacent channels must be identical in terms of technology, number of ranks, and size.
The BIOS setup provides an option to enable mirroring if the current DIMM population is valid
for channel mirroring. When memory mirroring is enabled, the BIOS attempts to configure the
memory system accordingly. If the BIOS finds that the DIMM population is not suitable for
mirroring, it falls back to the default Channel Independent mode with maximum
memory interleaving.
3.2.4.3.1 Minimum DDR3 DIMM Population for Channel Mirroring
Memory mirroring has the following minimum requirements:
Channel configuration: Mirroring requires the first two adjacent channels to be active.
Socket configuration: Mirroring requires that both socket 1 and socket 2 DIMM
population meets the requirements for mirroring mode. The platform BIOS configures the
system in mirroring mode only if both nodes qualify. The only exception to this rule is
socket 2 with all empty DIMM slots.
As a direct consequence of these requirements, the minimal DIMM population is {A1, B1}. In
this configuration, processor cores on socket 2 suffer memory latency due to usage of remote
memory from socket 1. An optimal DIMM population for channel mirroring in a DP server
platform is {A1, B1, D1, E1}. {A1, B1} must be identical and {D1, E1} must be identical.
In this configuration, DIMMs {A1, B1} and {D1, E1} operate as (primary copy, secondary copy)
pairs independent from each other. Therefore, the optimal number of DDR3 DIMMs for channel
mirroring is a multiple of four, arranged as mentioned above. The BIOS disables all non-
identical DDR3 DIMMs or pairs of DDR3 DIMMs across the channels to achieve symmetry and
balance between the channels.
3.2.4.3.2 Mirroring DIMM Population Rules Variance across Nodes
Memory mirroring in Intel
series processors based platforms is channel mirroring. Mirroring is not done across sockets, so
each socket may have a different memory configuration. Channel mirroring in socket 1 and
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Xeon
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Xeon Processor 5500 series and Intel
Intel order number: E64311-007
Intel® Compute Module MFS5520VI TPS
Processor 5600 series processors alternates
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Xeon
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Processor 5600
Revision 1.5