Reset And Miscellaneous Signals; Table 6-24 Reset And Miscellaneous Signals - Intel P4000 - DATASHEET REV 001 Datasheet

6.3

Reset and Miscellaneous Signals

Table 6-24.Reset and Miscellaneous Signals (Sheet 1 of 2)
Signal Name
SM_DRAMRST#
PM_EXT_TS#[0]
PM_EXT_TS#[1]
RESET_OBS#
BPM#[7:0]
74
DDR3 DRAM Reset: Reset signal from
processor to DRAM devices. One for all
channels or SO-DIMMs.
External Thermal Sensor Input: If the
system temperature reaches a dangerously
high value then this signal can be used to
trigger the start of system memory
throttling.
COMP0 Impedance compensation must be
terminated on the system board using a
precision resistor.
COMP1 Impedance compensation must be
terminated on the system board using a
precision resistor.
COMP2 Impedance compensation must be
terminated on the system board using a
precision resistor.
COMP3 Impedance compensation must be
terminated on the system board using a
precision resistor.
PM_SYNC Power Management Sync: A sideband
signal to communicate power management
status from the platform to the processor.
This signal is an indication of the processor
being reset.
RSTIN# Reset In: When asserted this signal will
asynchronously reset the processor logic.
This signal is connected to the PLTRST#
output of the PCH.
Breakpoint and Performance Monitor
Signals: Outputs from the processor that
indicate the status of breakpoints and
programmable counters used for monitoring
processor performance.
DBR# Debug Reset: Used only in systems where
no debug port is implemented on the system
board. DBR# is used by a debug port
interposer so that an in-target probe can
drive system reset. This signal only routes
through the package and does not connect to
the the processor silicon itself.
Description
Signal Description
Direction/Buffer
Type
O
DDR3
I
CMOS
I
A
I
A
I
A
I
A
I
CMOS
O
Asynchronous CMOS
I
CMOS
I/O
GTL
O
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