Intel E6600 - Core 2 Duo Dual-Core Processor Specification page 65

Errata
AI120. VM Exit due to Virtual APIC-Access May Clear RF
RF (Resume Flag), bit 16 of the EFLAGS/RFLAGS register, is used to restart
Problem:
instruction execution without getting an instruction breakpoint on the
instruction following a debug breakpoint exception. Due to this erratum, in a
system supporting Intel
due to Virtual APIC-Access (Advanced Programmable Interrupt Controller-
Access) the EFLAGS/RFLAGS saved in the VMCS (Virtual-Machine Control
Structure) may contain an RF value of 0.
Implication: When this erratum occurs, following a VM Exit due to a Virtual APIC-access,
the processor may unintentionally break on the subsequent instruction after
VM entry.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI121. Fixed Function Performance Counters MSR_PERF_FIXED_CTR1
(30AH) and MSR_PERF_FIXED_CTR2 (30BH) are Not Cleared When
the Processor is Reset
The Fixed Function Performance Counters that count the number of core
Problem:
cycles and reference cycles when the core is not in a halt state are not
cleared when the processor is reset.
Implication: The MSR_PERF_FIXED_CTR1 and MSR_PERF_FIXED_CTR2 counters may
contain unexpected values after reset.
Workaround: BIOS can workaround this erratum by clearing the counters at processor
initialization time.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI122. VTPR Access May Lead to System Hang
The logical processor may hang if an instruction performs a VTPR access and
Problem:
the next instruction to be executed is located on a different code page.
Implication: Software running VMX non-root operation may cause a logical processor to
hang if the virtual-machine monitor (VMM) sets both the "use TPR shadow"
and "virtualize APIC accesses" VM-execution controls.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI123. IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine Check
Error Reporting Enable Correctly
IA32_MC1_STATUS MSR (405H) bit[60] (EN- Error Enabled) is supposed to
Problem:
indicate whether the enable bit in the IA32_MC1_CTL MSR (404H) was set at
the time of the last update to the IA32_MC1_STATUS MSR. Due to this
®
Intel Core™2 Extreme Processor X6800 and
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
®
Virtualization Technology, when a VM Exit occurs
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