Intel E6600 - Core 2 Duo Dual-Core Processor Specification page 45

Errata
Implication: This scenario may only occur on a multiprocessor platform running an
operating system that performs "lazy" TLB shootdowns. The memory image
of the EFLAGS register on the page fault handler's stack prematurely contains
the final arithmetic flag values although the instruction has not yet
completed. Intel has not identified any operating systems that inspect the
arithmetic portion of the EFLAGS register during a page fault nor observed
this erratum in laboratory testing of software applications.
Workaround: No workaround is needed upon normal restart of the instruction, since this
erratum is transparent to the faulting code and results in correct instruction
behavior. Operating systems may ensure that no processor is currently
accessing a page that is scheduled to have its page permissions tightened or
have a page fault handler that ignores any incorrect state.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI63. LBR, BTS, BTM May Report a Wrong Address when an
Exception/Interrupt Occurs in 64-bit Mode
An exception/interrupt event should be transparent to the LBR (Last Branch
Problem:
Record), BTS (Branch Trace Store) and BTM (Branch Trace Message)
mechanisms. However, during a specific boundary condition where the
exception/interrupt occurs right after the execution of an instruction at the
lower canonical boundary (0x00007FFFFFFFFFFF) in 64-bit mode, the LBR
return registers will save a wrong return address with bits 63 to 48
incorrectly sign extended to all 1's. Subsequent BTS and BTM operations
which report the LBR will also be incorrect.
Implication: LBR, BTS and BTM may report incorrect information in the event of an
exception/interrupt.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI64. Returning to Real Mode from SMM with EFLAGS.VM Set May Result in
Unpredictable System Behavior
Returning back from SMM mode into real mode while EFLAGS.VM is set in
Problem:
SMRAM may result in unpredictable system behavior.
Implication: If SMM software changes the values of the EFLAGS.VM in SMRAM, it may
result in unpredictable system behavior. Intel has not observed this behavior
in commercially available software.
Workaround: SMM software should not change the value of EFLAGS.VM in SMRAM.
For the steppings affected, see the Summary Tables of Changes.
Status:
®
Intel Core™2 Extreme Processor X6800 and
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
45