Intel E6600 - Core 2 Duo Dual-Core Processor Specification page 14

NO B1 B2 L2
AI74 X X X
AI75 X X X
AI76 X X X
AI77 X X X
AI78 X X X
AI79 X X X
AI80 X X X
AI81 X X X
AI82 X X X
AI83 X X X
AI84 X X X
AI85 X X X
AI86 X X
AI87 X X X
AI88 X X X
AI89 X X X
AI90 X X X
AI91 X X X
AI92 X X X
AI93 X X X
AI94 X X X
AI95 X X X
14
M0 G0 Plan ERRATA
X X No Fix An Asynchronous MCE During a Far Transfer May Corrupt ESP
In Single-Stepping on Branches Mode, the BS Bit in the
X Fixed Pending-Debug-Exceptions Field of the Guest State Area will be
Incorrectly Set by VM-Exit on a MOV to CR8 Instruction
B0-B3 Bits in DR6 May Not be Properly Cleared After Code
X X No Fix
Breakpoint
BTM/BTS Branch-From Instruction Address May be Incorrect for
X X No Fix
Software Interrupts
Last Branch Records (LBR) Updates May be Incorrect After a
X X No Fix
Task Switch
REP Store Instructions in a Specific Situation may cause the
X Fixed
Processor to Hang
Performance Monitoring Events for L1 and L2 Miss May Not be
X X No Fix
Accurate
Store to WT Memory Data May be Seen in Wrong Order by Two
X X No Fix
Subsequent Loads
A MOV Instruction from CR8 Register with 16 Bit Operand Size
X X No Fix
Will Leave Bits 63:16 of the Destination Register Unmodified
Non-Temporal Data Store May be Observed in Wrong Program
X X No Fix
Order
Performance Monitor SSE Retired Instructions May Return
X X No Fix
Incorrect Values
Fault on ENTER Instruction May Result in Unexpected Values on
X X No Fix
Stack Frame
CPUID Reports Architectural Performance Monitoring Version 2
Fixed
is Supported, When Only Version 1 Capabilities are Available
Unaligned Accesses to Paging Structures May Cause the
X X No Fix
Processor to Hang
Microcode Updates Performed During VMX Non-root Operation
X X No Fix
Could Result in Unexpected Behavior
INVLPG Operation for Large (2M/4M) Pages May be Incomplete
X X No Fix
under Certain Conditions
Page Access Bit May be Set Prior to Signaling a Code Segment
X X No Fix
Limit Fault
Update of Attribute Bits on Page Directories without Immediate
X Fixed
TLB Shootdown May Cause Unexpected Processor Behavior
X Fixed Invalid Instructions May Lead to Unexpected Behavior
EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after
X X No Fix
Shutdown
Performance Monitoring Counter MACRO_INSTS.DECODED May
X Fixed
Not Count Some Decoded Instructions
The Stack Size May be Incorrect as a Result of VIP/VIF Check
X Fixed
on SYSEXIT and SYSRET
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Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Summary Tables of Changes
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Intel Core™2 Extreme Processor X6800 and
Specification Update