Intel E6600 - Core 2 Duo Dual-Core Processor Specification page 43

Errata
AI58. CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal
48
to 2 May Terminate Early
In 64-bit Mode CMPSB, LODSB, or SCASB executed with a repeat prefix and
Problem:
count greater than or equal to 2
may result in one of the following.
The last iteration not being executed
•
Signaling of a canonical limit fault (#GP) on the last iteration
•
Implication: While in 64-bit mode, with count greater or equal to 2
operations CMPSB, LODSB or SCASB may terminate without completing the
last iteration. Intel has not observed this erratum with any commercially
available software.
Workaround: Do not use repeated string operations with RCX greater than or equal to 2
For the steppings affected, see the Summary Tables of Changes.
Status:
AI59. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types may use an
Incorrect Data Size or Lead to Memory-Ordering Violations.
Under certain conditions as described in the Software Developers Manual
Problem:
section "Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon,
and P6 Family Processors" the processor performs REP MOVS or REP STOS as
fast strings. Due to this erratum fast string REP MOVS/REP STOS instructions
that cross page boundaries from WB/WC memory types to UC/WP/WT
memory types, may start using an incorrect data size or may observe
memory ordering violations.
Implication: Upon crossing the page boundary the following may occur, dependent on the
new page memory type:
• UC the data size of each write will now always be 8 bytes, as opposed to the
original data size.
• WP the data size of each write will now always be 8 bytes, as opposed to the
original data size and there may be a memory ordering violation.
• WT there may be a memory ordering violation.
Workaround: Software should avoid crossing page boundaries from WB or WC memory
type to UC, WP or WT memory type within a single REP MOVS or REP STOS
instruction that will execute with fast strings enabled.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI60. MOV To/From Debug Registers Causes Debug Exception
When in V86 mode, if a MOV instruction is executed to/from on debug
Problem:
register, a general-protection exception (#GP) should be generated.
However, in the case when the general detect enable flag (GD) bit is set, the
observed behavior is that a debug exception (#DB) is generated instead.
®
Intel Core™2 Extreme Processor X6800 and
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
48
may terminate early. Early termination
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, repeat string
48
.
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