Intel E6600 - Core 2 Duo Dual-Core Processor Specification page 11

Summary Tables of Changes
NO B1 B2 L2
AI10 X X X
AI11 X X X
AI12 X X X
AI13 X X X
AI14 X X X
AI15 X X X
AI16 X X X
AI17 X X X
AI18 X X X
AI19 X X X
AI20 X X X
AI21 X X X
AI22 X X X
AI23 X X X
AI24 X X X
AI25 X X X
AI26 X X X
AI27 X X X
AI28 X X X
AI29 X X X
AI30 X X
®
Intel Core™2 Extreme Processor X6800 and
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
M0 G0 Plan ERRATA
Single Step Interrupts with Floating Point Exception Pending
X X No Fix
May Be Mishandled
A Write to an APIC Register Sometimes May Appear to Have
X X No Fix
Not Occurred
Programming the Digital Thermal Sensor (DTS) Threshold May
X X No Fix
Cause Unexpected Thermal Interrupts
Count Value for Performance-Monitoring Counter
X X No Fix
PMH_PAGE_WALK May be Incorrect
X X No Fix LER MSRs May be Incorrectly Updated
Performance Monitoring Events for Retired Instructions (C0H)
X X No Fix
May Not Be Accurate
Performance Monitoring Event For Number Of Reference Cycles
X X No Fix When The Processor Is Not Halted (3CH) Does Not Count
According To The Specification
Using 2M/4M Pages When A20M# Is Asserted May Result in
X X No Fix
Incorrect Address Translations
Writing Shared Unaligned Data that Crosses a Cache Line
X X No Fix without Proper Semaphores or Barriers May Expose a Memory
Ordering Issue
Code Segment Limit Violation May Occur on 4 Gigabyte Limit
X X No Fix
Check
X Fixed FP Inexact-Result Exception Flag May Not Be Set
Global Pages in the Data Translation Look-Aside Buffer (DTLB)
X Fixed May Not Be Flushed by RSM instruction before Restoring the
Architectural State from SMRAM
Sequential Code Fetch to Non-canonical Address May have
X Fixed
Non-deterministic Results
VMCALL to Activate Dual-monitor Treatment of SMIs and SMM
X Fixed
Ignores Reserved Bit settings in VM-exit Control Field
X X No Fix The PECI Controller Resets to the Idle State
Some Bus Performance Monitoring Events May Not Count Local
X X No Fix
Events under Certain Conditions
Premature Execution of a Load Operation Prior to Exception
X X No Fix
Handler Invocation
General Protection (#GP) Fault May Not Be Signaled on Data
X X No Fix
Segment Limit Violation above 4-G Limit
X X No Fix EIP May be Incorrect after Shutdown in IA-32e Mode
#GP Fault is Not Generated on Writing IA32_MISC_ENABLE
X X No Fix
[34] When Execute Disable Bit is Not Supported
(E)CX May Get Incorrectly Updated When Performing Fast
Fixed String REP MOVS or Fast String REP STOS With Large Data
Structures
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