Intel E6600 - Core 2 Duo Dual-Core Processor Specification page 32

The following Bus Performance Monitoring events will not count power
management related events for local core-specificity:
BUS_TRANS_ IO (Event: 6CH) – Will not count I/O level reads resulting from
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package-resolved C-state
BUS_TRANS_ANY (Event: 70H) – Will not count Stop-Grants
•
Implication: The count values for the affected events may be lower than expected. The
degree of undercount depends on the occurrence of erratum conditions while
the affected events are active.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI26. Premature Execution of a Load Operation Prior to Exception Handler
Invocation
If any of the below circumstances occur, it is possible that the load portion of
Problem:
the instruction will have executed before the exception handler is entered.
If an instruction that performs a memory load causes a code segment limit
•
violation.
If a waiting X87 floating-point (FP) instruction or MMX™ technology (MMX)
•
instruction that performs a memory load has a floating-point exception pending.
If an MMX or SSE/SSE2/SSE3/SSSE3 extensions (SSE) instruction that performs a
•
memory load and has either CR0.EM=1 (Emulation bit set), or a floating-point
Top-of-Stack (FP TOS) not equal to 0, or a DNA exception pending.
Implication: In normal code execution where the target of the load operation is to write
back memory there is no impact from the load being prematurely executed,
or from the restart and subsequent re-execution of that instruction by the
exception handler. If the target of the load is to uncached memory that has a
system side-effect, restarting the instruction may cause unexpected system
behavior due to the repetition of the side-effect. Particularly, while CR0.TS
[bit 3] is set, a MOVD/MOVQ with MMX/XMM register operands may issue a
memory load before getting the DNA exception.
Workaround: Code which performs loads from memory that has side-effects can effectively
workaround this behavior by using simple integer-based load instructions
when accessing side-effect memory and by ensuring that all code is written
such that a code segment limit violation cannot occur as a part of reading
from side-effect memory.
AI27. General Protection (#GP) Fault May Not Be Signaled on Data
Segment Limit Violation above 4-G Limit
In 32-bit mode, memory accesses to flat data segments (base = 00000000h)
Problem:
that occur above the 4G limit (0ffffffffh) may not signal a #GP fault.
Implication: When such memory accesses occur in 32-bit mode, the system may not issue
a #GP fault.
32 Intel
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
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Core™2 Extreme Processor X6800 and
Specification Update
Errata