Intel E6600 - Core 2 Duo Dual-Core Processor Specification page 16

NO B1 B2 L2
AI117 X X X
AI118 X X X
AI119 X X X
AI120 X X X
AI121
AI122
AI123
AI124 X X X
AI125 X X X
AI126 X X X
AI127 X X X
AI128 X X X
AI129 X X X
Number
-
Number
AI1
Number
-
16
M0 G0 Plan ERRATA
A WB Store Following a REP STOS/MOVS or FXSAVE May Lead
X X No Fix
to Memory-Ordering Violations
VM Exit with Exit Reason "TPR Below Threshold" Can Cause the
X X No Fix Blocking by MOV/POP SS and Blocking by STI Bits to be
Cleared in the Guest Interruptibility-State Field
Using Memory Type Aliasing with Cacheable and WC Memory
X X No Fix
Types May Lead to Memory Ordering Violations
X X No Fix VM Exit due to Virtual APIC-Access May Clear RF
Fixed Function Performance Counters MSR_PERF_FIXED_CTR1
X Fixed (30AH) and MSR_PERF_FIXED_CTR2 (30BH) are Not Cleared
When the Processor is Reset
X Fixed VTPR Access May Lead to System Hang
IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine
X Fixed
Check Error Reporting Enable Correctly
RSM Instruction Execution under Certain Conditions May Cause
X X No Fix
Processor Hang or Unexpected Instruction Execution Results
Fixed NMIs May Not Be Blocked by a VM-Entry Failure
Benign Exception after a Double Fault May Not Cause a Triple
X X No Fix
Fault Shutdown
A VM Exit Due to a Fault While Delivering a Software Interrupt
X X No Fix
May Save Incorrect Data into the VMCS
A VM Exit Occuring in IA-32e Mode May Not Produce a VMX
X X No Fix
Abort When Expected
A 64-bit Register IP-relative Instruction May Return
X X No Fix
Unexpected Results
There are no Specification Changes in this Specification Update revision.
SPECIFICATION CLARIFICATIONS
Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation
There are no Documentation Changes in this Specification Update revision.
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
SPECIFICATION CHANGES
DOCUMENTATION CHANGES
§
®
Intel Core™2 Extreme Processor X6800 and
Summary Tables of Changes
Specification Update