Intel E6600 - Core 2 Duo Dual-Core Processor Specification page 35

Errata
Implication: In this case, the phrase "unexpected or unpredictable execution behavior"
encompasses the generation of most of the exceptions listed in the Intel
Architecture Software Developer's Manual Volume 3: System Programming
Guide, including a General Protection Fault (GPF) or other unexpected
behaviors. In the event that unpredictable execution causes a GPF the
application executing the unsynchronized XMC operation would be terminated
by the operating system.
Workaround: In order to avoid this erratum, programmers should use the XMC
synchronization algorithm as detailed in the Intel Architecture Software
Developer's Manual Volume 3: System Programming Guide, Section:
Handling Self- and Cross-Modifying Code.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI34. MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum
Frequency Clock Count (IA32_MPERF) May Contain Incorrect Data
after a Machine Check Exception (MCE)
When an MCE occurs during execution of a RDMSR instruction for MSRs
Problem:
Actual Frequency Clock Count (IA32_APERF) or Maximum Frequency Clock
Count (IA32_MPERF), the current and subsequent RDMSR instructions for
these MSRs may contain incorrect data.
Implication: After an MCE event, accesses to the IA32_APERF and IA32_MPERF MSRs may
return incorrect data. A subsequent reset will clear this condition.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI35. Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR
Image Leads to Partial Memory Update
A partial memory state save of the 512-byte FXSAVE image or a partial
Problem:
memory state restore of the FXRSTOR image may occur if a memory address
exceeds the 64KB limit while the processor is operating in 16-bit mode or if a
memory address exceeds the 4GB limit while the processor is operating in
32-bit mode.
Implication: FXSAVE/FXRSTOR will incur a #GP fault due to the memory limit violation as
expected but the memory state may be only partially saved or restored.
Workaround: Software should avoid memory accesses that wrap around the respective 16-
bit and 32-bit mode memory limits.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI36. Split Locked Stores May not Trigger the Monitoring Hardware
Logical processors normally resume program execution following the MWAIT,
Problem:
when another logical processor performs a write access to a WB cacheable
address within the address range used to perform the MONITOR operation.
®
Intel Core™2 Extreme Processor X6800 and
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
35