Intel E6600 - Core 2 Duo Dual-Core Processor Specification page 15

Summary Tables of Changes
NO B1 B2 L2
AI96 X X X
AI97 X X X
AI98 X X X
AI99 X X X
AI100 X X X
AI101 X
AI102 X X X
AI103 X X X
AI104 X X X
AI105 X X X
AI106 X X X
AI107 X X X
AI108
AI109 X X X
AI110 X X X
AI111
AI112 X X X
AI113
AI114
AI115 X X X
AI116 X X X
®
Intel Core™2 Extreme Processor X6800 and
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
M0 G0 Plan ERRATA
Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is
X X No Fix
Counted Incorrectly for PMULUDQ Instruction
Storage of PEBS Record Delayed Following Execution of MOV
X X No Fix
SS or STI
Store Ordering May be Incorrect between WC and WP Memory
X X No Fix
Types
Updating Code Page Directory Attributes without TLB
X X No Fix
Invalidation May Result in Improper Handling of Code #PF
Performance Monitoring Event CPU_CLK_UNHALTED.REF May
X Fixed Not Count Clock Cycles According to the Processors Operating
Frequency
(E)CX May Get Incorrectly Updated When Performing Fast
X Fixed
String REP STOS With Large Data Structures
Performance Monitoring Event BR_INST_RETIRED May Count
X Fixed
CPUID Instructions as Branches
Performance Monitoring Event MISALIGN_MEM_REF May Over
X X No Fix
Count
A REP STOS/MOVS to a MONITOR/MWAIT Address Range May
X X No Fix
Prevent Triggering of the Monitoring Hardware
False Level One Data Cache Parity Machine-Check Exceptions
Fixed
May be Signaled
A Memory Access May Get a Wrong Memory Type Following a
X X No Fix
#GP due to WRMSR to an MTRR Mask
PMI While LBR Freeze Enabled May Result in Old/Out-of-date
X X No Fix
LBR Information
VMCALL failure due to corrupt MSEG location may cause VM
X Fixed
Exit to load the machine state incorrectly
Overlap of an Intel
X Fixed
DS Save Area May Lead to Unpredictable Behavior
VTPR Write Access During Event Delivery May Cause an APIC-
X X No Fix
Access VM Exit
X X No Fix BIST Failure After Reset
Performance Monitoring Event FP_MMX_TRANS_TO_MMX May
X X No Fix
Not Count Some Transitions
When One Core Executes SEXIT the Other Core's Last Branch
X No Fix
Recording May be Incorrect
A GETSEC[ENTERACCS] Instruction Executed Immediately after
X No Fix
GETSEC[WAKEUP] Instruction May Result in a Processor Hang
Instruction Fetch May Cause a Livelock During Snoops of the L1
X X No Fix
Data Cache
Use of Memory Aliasing with Inconsistent Memory Type may
X X No Fix
Cause a System Hang or a Machine Check Exception
®
VT APIC Access Page in a Guest with the
15