Intel E6600 - Core 2 Duo Dual-Core Processor Specification page 13

Summary Tables of Changes
NO B1 B2 L2
AI52 X X X
AI53 X X X
AI54 X X X
AI55 X X X
AI56 X X X
AI57 X X X
AI58 X X X
AI59 X X X
AI60 X X X
AI61 X X X
AI62 X X X
AI63 X X X
AI64 X X X
AI65 X X X
AI66 X X X
AI67 X X X
AI68 X X X
AI69 X X X
AI70 X X X
AI71 X X X
AI72 X X X
AI73 X X X
®
Intel Core™2 Extreme Processor X6800 and
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
M0 G0 Plan ERRATA
Last Branch Records (LBR) Updates May be Incorrect after a
X X No Fix
Task Switch
IO_SMI Indication in SMRAM State Save Area May Be Set
X X No Fix
Incorrectly
X X No Fix INIT Does Not Clear Global Entries in the TLB
Using Memory Type Aliasing with Memory Types WB/WT May
X Fixed
Lead to Unpredictable Behavior
Update of Read/Write (R/W) or User/Supervisor (U/S) or
X Fixed Present (P) Bits without TLB Shootdown May Cause Unexpected
Processor Behavior
X Fixed BTS Message May Be Lost When the STPCLK# Signal is Active
CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater
X X No Fix
or Equal to 2
REP MOVS/STOS Executing with Fast Strings Enabled and
Crossing Page Boundaries with Inconsistent Memory Types may
X X No Fix
use an Incorrect Data Size or Lead to Memory-Ordering
Violations.
X X No Fix MOV To/From Debug Registers Causes Debug Exception
Debug Register May Contain Incorrect Information on a MOVSS
X Fixed
or POPSS Instruction Followed by SYSRET
EFLAGS Discrepancy on a Page Fault After a Multiprocessor TLB
X X No Fix
Shootdown
LBR, BTS, BTM May Report a Wrong Address when an
X X No Fix
Exception/Interrupt Occurs in 64-bit Mode
Returning to Real Mode from SMM with EFLAGS.VM Set May
X X No Fix
Result in Unpredictable System Behavior
A Thermal Interrupt is Not Generated when the Current
X X No Fix
Temperature is Invalid
VMLAUNCH/VMRESUME May Not Fail when VMCS is
X Fixed
Programmed to Cause VM Exit to Return to a Different Mode
IRET under Certain Conditions May Cause an Unexpected
X X No Fix
Alignment Check Exception
X X No Fix Performance Monitoring Event FP_ASSIST May Not be Accurate
CPL-Qualified BTS May Report Incorrect Branch-From
X Fixed
Instruction Address
PEBS Does Not Always Differentiate Between CPL-Qualified
X Fixed
Events
X X No Fix PMI May Be Delayed to Next PEBS Event
PEBS Buffer Overflow Status Will Not be Indicated Unless
X Fixed
IA32_DEBUGCTL[12] is Set
The BS Flag in DR6 May be Set for Non-Single-Step #DB
X X No Fix
Exception
48
May Terminate Early
13