Intel E6600 - Core 2 Duo Dual-Core Processor Specification page 10

AK = Intel
Core™2 Quad processor Q6 00 sequence
AL = Dual-Core Intel
AM = Intel
AN = Intel
AO = Quad-Core Intel
AP = Dual-Core Intel
AQ = Intel
AR = Intel
AS = Intel
AV = Intel
Q9000 series
AW = Intel
AX = Quad-Core Intel
AY= Dual-Core Intel
AZ = Intel
Process
AAA = Quad-Core Intel
AAB = Dual-Core Intel
AAC = Intel
AAD = Intel
AAE = Intel
The Specification Updates for the Pentium
other Intel products do not use this convention.
NO B1 B2 L2
AI1 X X X
AI2 X X X
AI3 X X X
AI4 X X X
AI5 X X X
AI6 X X X
AI7 X X X
AI8 X X X
AI9 X X X
10
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Core™2 Extreme quad-core processor QX6000 sequence and Intel
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Xeon processor 7100 series
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Celeron processor 400 sequence
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Pentium dual-core processor
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Xeon processor 3200 series
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Xeon processor 3000 series
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Pentium dual-core desktop processor E2000 sequence
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Celeron processor 500 series
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Xeon processor 7200, 7300 series
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Core™2 Extreme processor QX9650 and Intel
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Core™ 2 Duo processor E8000 series
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Xeon processor 5400 series
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Xeon processor 5200 series
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Core™2 Duo Processor and Intel
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Xeon processor 3300 series
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Xeon E3110 Processor
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Celeron dual-core processor E1000 series
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Core™2 Extreme Processor QX9775Δ
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Atom™ processor Z5xx series
M0 G0 Plan ERRATA
Writing the Local Vector Table (LVT) when an Interrupt is
X X No Fix
Pending May Cause an Unexpected Interrupt
LOCK# Asserted During a Special Cycle Shutdown Transaction
X X No Fix
May Unexpectedly De-assert
Address Reported by Machine-Check Architecture (MCA) on
X X No Fix
Single-bit L2 ECC Errors May be Incorrect
VERW/VERR/LSL/LAR Instructions May Unexpectedly Update
X X No Fix
the Last Exception Record (LER) MSR
DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
X X No Fix Instruction May Incorrectly Increment Performance Monitoring
Count for Saturating SIMD Instructions Retired (Event CFH)
SYSRET May Incorrectly Clear RF (Resume Flag) in the RFLAGS
X Fixed
Register
General Protection Fault (#GP) for Instructions Greater than 15
X X No Fix
Bytes May be Preempted
Pending x87 FPU Exceptions (#MF) Following STI May Be
X X No Fix
Serviced Before Higher Priority Interrupts
X X No Fix The Processor May Report a #TS Instead of a #GP Fault
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Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Summary Tables of Changes
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Core™2 Quad processor
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Core™2 Extreme Processor on 45-nm
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processor, Pentium
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Intel Core™2 Extreme Processor X6800 and
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Pro processor, and
Specification Update