Intel E6600 - Core 2 Duo Dual-Core Processor Specification page 47

Errata
AI68. Performance Monitoring Event FP_ASSIST May Not be Accurate
Performance monitoring event FP_ASSIST (11H) may be inaccurate as assist
Problem:
events will be counted twice per actual assist in the following specific cases:
FADD and FMUL instructions with a NaN(Not a Number) operand and a memory
•
operand
FDIV instruction with zero operand value in memory
•
In addition, an assist event may be counted when DAZ (Denormals-Are-Zeros) and
FTZ (Flush-To-Zero) flags are turned on even though no actual assist occurs.
Implication: The counter value for the performance monitoring event FP_ASSIST (11H)
may be larger than expected. The size of the error is dependent on the
number of occurrences of the above conditions while the event is active.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI69. CPL-Qualified BTS May Report Incorrect Branch-From Instruction
Address
CPL (Current Privilege Level)-qualified BTS (Branch Trace Store) may report
Problem:
incorrect branch-from instruction address under the following conditions:
Either BTS_OFF_OS[9] or BTS_OFF_USR[10] is selected in IA32_DEBUGCTLC MSR
•
(1D9H)
Privilege-level transitions occur between CPL > 0 and CPL 0 or vice versa.
•
Implication: Due to this erratum, the From address reported by BTS may be incorrect for
the described conditions.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI70. PEBS Does Not Always Differentiate Between CPL-Qualified Events
Performance monitoring counter configured to sample PEBS (Precise Event
Problem:
Based Sampling) events at a certain privilege level may count samples at the
wrong privilege level.
Implication: Performance monitoring counter may be higher than expected for CPL-
qualified events. Do not use performance monitoring counters for precise
event sampling when the precise event is dependent on the CPL value.
Workaround: Do not use performance monitoring counters for precise event sampling when
the precise event is dependent on the CPL value.
For the steppings affected, see the Summary Tables of Changes.
Status:
®
Intel Core™2 Extreme Processor X6800 and
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
47