Intel E6600 - Core 2 Duo Dual-Core Processor Specification page 27

Errata
For the steppings affected, see the Summary Tables of Changes.
Status:
AI13. Count Value for Performance-Monitoring Counter PMH_PAGE_WALK
May be Incorrect
Performance-Monitoring Counter PMH_PAGE_WALK is used to count the
Problem:
number of page walks resulting from Data Translation Look-Aside Buffer
(DTLB) and Instruction Translation Look-Aside (ITLB) misses. Under certain
conditions, this counter may be incorrect.
Implication: There may be small errors in the accuracy of the counter.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI14. LER MSRs May be Incorrectly Updated
The LER (Last Exception Record) MSRs, MSR_LER_FROM_LIP
Problem:
(1DDH) and MSR_LER_TO_LIP (1DEH) may contain incorrect values after any
of the following:
Either STPCLK#, NMI (NonMaskable Interrupt) or external interrupts
•
CMP or TEST instructions with an uncacheable memory operand followed by a
•
conditional jump
STI/POP SS/MOV SS instructions followed by CMP or TEST instructions
•
and then by a conditional jump
Implication: When the conditions for this erratum occur, the value of the LER MSRs may
be incorrectly updated.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AI15. Performance Monitoring Events for Retired Instructions (C0H) May
Not Be Accurate
The INST_RETIRED performance monitor may miscount retired instructions
Problem:
as follows:
Repeat string and repeat I/O operations are not counted when a hardware
•
interrupt is received during or after the last iteration of the repeat flow.
• VMLAUNCH and VMRESUME instructions are not counted.
HLT and MWAIT instructions are not counted. The following instructions, if
•
executed during HLT or MWAIT events, are also not counted:
a) RSM from a C-state SMI during an MWAIT instruction.
b) RSM from an SMI during a HLT instruction.
®
Intel Core™2 Extreme Processor X6800 and
®
Intel Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
27