Figure 6. Memory Layout; Table 1. I 2 C Addresses For Memory Module Smb - Intel MFSYS25V2 Specification

Intel® Compute Module MFS5000SI TPS
Branch 0
To boot the system, the system BIOS on the server board uses a dedicated I
information needed to program the MCH memory registers. The following table provides the I
addresses for each DIMM slot.
3.1.3.1 Memory RASUM Features
The MCH supports several memory RASUM (Reliability, Availability, Serviceability, Usability, and
Manageability) features. These features include the Intel
SDDC) for memory error detection and correction, Memory Scrubbing, Retry on Correctable Errors,
Memory Built In Self Test, DIMM Sparing, and Memory Mirroring. For more information regarding these
®
features, see the Intel
5000 Series Chipsets Server Board Family Datasheet.
1
DIMM Sparing and Memory Mirroring features will be made available post production launch with a BIOS update.
Revision 1.4
Branch 1

Figure 6. Memory Layout

2
Table 1. I C Addresses for Memory Module SMB
Device
DIMM A1
DIMM A2
DIMM B1
DIMM B2
DIMM C1
DIMM C2
DIMM D1
DIMM D2
1
Intel order number: E15154-007
Channel B
Channel A
Address
0xA0
0xA2
0xA0
0xA2
0xA0
0xA2
0xA0
0xA2
®
x4 Single Device Data Correction (Intel
2BFunctional Architecture
Channel C
Channel D
TP02299
2
C bus to retrieve DIMM
2
C
®
x4
9