Functional Architecture; Figure 4. Compute Module Functional Block Diagram - Intel MFSYS25V2 Specification

2BFunctional Architecture Intel® Compute Module MFS5000SI TPS
3.

Functional Architecture

® ®
The architecture and design of the Intel Compute Module MFS5000SI is based on the Intel 5000
®
Chipset Family. The chipset is designed for systems based on the Dual-Core and Quad-Core Intel
®
Xeon processor 5000 sequence with system bus speeds of 667 MHz, 1066 MHz, and 1333 MHz. The
chipset is made up of two main components: the Memory Controller Hub (MCH) for the host bridge and
®
the Intel 6321ESB I/O controller hub for the I/O subsystem. This chapter provides a high-level
description of the functionality associated with each chipset component and the architectural blocks that
of the
make up the server board. For more in-depth detail of the functionality for each chipset
®
components and each of the functional architecture blocks, see the Intel
5000 Series Chipsets Server
Board Family Datasheet.

Figure 4. Compute Module Functional Block Diagram

®
Note: The previous diagram uses the Intel 5000P MCH as a general reference designator for MCH
components supported on this server board.
Revision 1.4
6
Intel order number: E15154-007