Network Interface Controller (Nic); Intel I/O Acceleration Technology; Mac Address Definition; Super I/O - Intel MFSYS25V2 Specification

Intel® Compute Module MFS5000SI TPS
3.4

Network Interface Controller (NIC)

Network interface support is provided from the built-in Dual GbE MAC features of the Intel
Controller Hub. These interfaces are routed over the midplane board to the Ethernet switch module in the
rear of the system. These interfaces are used in SERDES mode and do not require a Physical Layer
Transceiver (PHY). These ports provide the server board with support for dual LAN ports designed for
10/100/1000 Mbps operation.
Each Network Interface Controller (NIC) drives a single LED located on the front edge of the board. The
link/activity LED indicates network connection when on, and Transmit/Receive activity when blinking.
3.4.1 Intel I/O Acceleration Technology
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Intel I/O Acceleration Technology (I/OAT) moves network data more efficiently through Dual-Core and
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Quad-Core Intel Xeon
responsiveness across diverse operating systems and virtualized environments. Intel
network application responsiveness by unleashing the power of Dual-Core and Quad-Core Intel
processors 5000 sequence through more efficient network data movement and reduced system
overhead. Intel multi-port network adapters with Intel
consolidation and virtualization through stateless network acceleration that seamlessly scales across
multiple ports and virtual machines. Intel
tight integration into popular operating systems and virtual machine monitors, avoiding the support risks
of third-party network stacks and preserving existing network requirements, such as teaming and failover.
3.4.2

MAC Address Definition

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Each Intel Compute Module MFS5000SI has four MAC addresses assigned to it at the Intel factory.
During the manufacturing process, each server board will have a white MAC address sticker placed on
the board. The sticker will display the MAC address in both barcode and alpha numeric formats. The
printed MAC address is assigned to NIC 1 on the server board. NIC 2 is assigned the NIC 1 MAC
address + 1.
Two additional MAC addresses are assigned to the Integrated Baseboard Management Controller (BMC)
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embedded in the Intel 6321ESB I/O Controller Hub. These MAC addresses are used by the Integrated
BMC's embedded network stack to enable IPMI remote management over LAN. BMC LAN Channel 1 is
assigned the NIC1 MAC address + 2, and BMC LAN Channel 2 is assigned the NIC1 MAC address + 3.
3.5

Super I/O

Legacy I/O support is provided by using a National Semiconductor* PC87427 Super I/O device. This chip
contains all of the necessary circuitry to support the following functions:
GPIOs
One serial port (internal and used for debug only)
Wake-up control
3.5.1.1 Serial Ports
The server board provides one serial port through an internal DH-10 serial header (J1B1) to be used for
debug purposes only. The serial interface follows the standard RS-232 pin-out as defined in the following
table.
Revision 1.4
processors 5000 sequence-based servers for improved application
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I/OAT provides safe and flexible network acceleration through
Intel order number: E15154-007
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I/OAT provide high-performance I/O for server
2BFunctional Architecture
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6321ESB I/O
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I/OAT improves
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Xeon
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