Holtek BS66F340C Manual page 89

BS66F340C/BS66F350C/BS66F360C
Touch A/D Flash MCU
Any register value, other than the four defined LVR values above, will also result in the
generation of an MCU reset. The reset operation will be activated after a delay time,
t
SRESET
• RSTFC Register
Bit 7
Name —
R/W —
POR —
Bit 7~4 Unimplemented, read as "0"
Bit 3 RSTF: Reset control register software reset flag
Refer to the Internal Reset Control section.
Bit 2 LVRF: LVR function reset flag
0: Not occurred
1: Occurred
This bit is set high when a specific Low Voltage Reset condition occurs. This bit can
only be cleared to zero by the application program.
Bit 1 LRF: LVRC register software reset flag
0: Not occurred
1: Occurred
This bit is set high if the LVRC register contains any non-defined LVR voltage register
values. This in effect acts like a software-reset function. This bit can only be cleared to
zero by the application program.
Bit 0 WRF: WDTC register software reset flag
Refer to the Watchdog Timer Control Register section.
IAP Reset
When a specific value of "55H" is written into the FC1 register, a reset signal will be generated to
reset the whole device. Refer to the In Application Programming section for more associated details.
Watchdog Time-out Reset during Normal Operation
After a Watchdog time-out reset during normal operations in the FAST or SLOW mode, the
Watchdog time-out flag TO will be set to "1".
Watchdog Time-out Reset during SLEEP or IDLE Mode
The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds
of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack
Pointer will be cleared to "0" and the TO flag will be set to "1". Refer to the System Start Up Time
Characteristics for t
Rev. 1.11
. However in this situation the register contents will be reset to the POR value.
6 5
— —
— —
— —
WDT Time-out
Internal Reset
WDT Time-out Reset during Normal Operation Timing Chart
details.
SST
WDT Time-out
Internal Reset
WDT Time-out Reset during SLEEP or IDLE Mode Timing Chart
89
4 3 2
— RSTF LVRF
— R/W R/W
— 0 x
t
RSTD
t
SST
1 0
LRF WRF
R/W R/W
0 0
"x": unknown
November 09, 2023