Holtek BS66F340C Manual page 125

BS66F340C/BS66F350C/BS66F360C
Touch A/D Flash MCU
Compact Type TM Operating Modes
The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode,
PWM Output Mode or Timer/Counter Mode. The operating mode is selected using the CTnM1 and
CTnM0 bits in the CTMnC1 register.
Compare Match Output Mode
To select this mode, bits CTnM1 and CTnM0 in the CTMnC1 register, should be set to 00
respectively. In this mode once the counter is enabled and running it can be cleared by three
methods. These are a counter overflow, a compare match from Comparator A and a compare match
from Comparator P. When the CTnCCLR bit is low, there are two ways in which the counter can be
cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all
zero which allows the counter to overflow. Here both CTMnAF and CTMnPF interrupt request flags
for Comparator A and Comparator P respectively, will both be generated.
If the CTnCCLR bit in the CTMnC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the CTMnAF interrupt request flag will be
generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when
CTnCCLR is high no CTMnPF interrupt request flag will be generated. If the CCRA bits are all
zero, the counter will overflow when it reaches its maximum 10-bit, 3FF Hex, value, however here
the CTMnAF interrupt request flag will not be generated.
As the name of the mode suggests, after a comparison is made, the CTMn output pin will change
state. The CTMn output pin condition however only changes state when a CTMnAF interrupt
request flag is generated after a compare match occurs from Comparator A. The CTMnPF interrupt
request flag, generated from a compare match occurs from Comparator P, will have no effect on
the CTMn output pin. The way in which the CTMn output pin changes state are determined by
the condition of the CTnIO1 and CTnIO0 bits in the CTMnC1 register. The CTMn output pin can
be selected using the CTnIO1 and CTnIO0 bits to go high, to go low or to toggle from its present
condition when a compare match occurs from Comparator A. The initial condition of the CTMn
output pin, which is setup after the CTnON bit changes from low to high, is setup using the CTnOC
bit. Note that if the CTnIO1 and CTnIO0 bits are zero then no pin change will take place.
Rev. 1.11 125 November 09, 2023