2.13
LEDs
There are three active‐low user LEDs on the Mercury+ XU7 SoC module ‐ two of them are connected to
the PS and one connected to the PL.
Signal Name
PS_LED0#
PS_LED1#
PL_LED2#
Table 21: User LEDs
The module is also equipped with two status LEDs, which offer details on the configuration process for
debugging purposes.
Signal Name
Signal Location
PS_ERROR
P21
PS_STATUS
P22
Table 22: Status LEDs
2.14
DDR4 SDRAM ﴾PS﴿
There are two DDR4 SDRAM channels on the Mercury+ XU7 SoC module: one attached directly to the
PS side ﴾which is available only as a shared resource to the PL side﴿ and one attached directly to the PL side.
The DDR4 SDRAM connected to the PS is mapped to I/O bank 504. The memory configuration on the
Mercury+ XU7 SoC module supports ECC error detection and correction; the correction code type used
is single bit error correction and double bit error detection ﴾SEC‐DED﴿.
Five 16‐bit memory chips are used to build an 72‐bit wide memory ﴾8 bits are unused﴿: 64 bits for data
and 8 bits for ECC.
The maximum memory bandwidth on the Mercury+ XU7 SoC module is:
2'400 Mbit/s
64 bit = 19'200 MB/s
2.14.1
DDR4 SDRAM Characteristics
Table
23
describes the memory availability and configuration on the Mercury+ XU7 SoC module.
Module
ME‐XU7‐D11E
ME‐XU7‐D12E
Table 23: DDR4 SDRAM (PS) Characteristics
D‐0000‐443‐001
Package Pin
J16
G16
AG9
Pin Name
PS_ERROR_OUT
PS_ERROR_STATUS
Density
4 Gbit
8 Gbit
Pin Name
MIO[24]
MIO[25]
IO_T1U_N12_64
Comment
Refer to Zynq UltraScale+ MPSoC Technical
Reference Manual [21]
Refer to Zynq UltraScale+ MPSoC Technical
Reference Manual [21]
35 /
61
Comment
User function / active‐low
User function / active‐low
User function / active‐low
Configuration
256 M
16 bit
512 M
16 bit
Version 10, 30.01.2024
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