Multi-Gigabit Transceiver ﴾Mgt - Enclustra Mercury+ XU7 User Manual

Parameter
VCC_ADC
VREF_ADC
ADC Range
Sampling Rate per ADC
Total number of channels available on the module connector
Table 11: System Monitor (PL) Parameters
2.9 Multi‐Gigabit Transceiver ﴾MGT﴿
There are two types of multi‐gigabit transceivers available on the Mercury+ XU7 SoC module: GTH
transceivers ﴾connected to the PL﴿ and GTR transceivers ﴾connected to the PS﴿.
Tip
For optimal performance of high‐speed interfaces, for example, PCIe, use redrivers on the base board.
Tip
The maximum data rate on the MGT transceivers on the Mercury+ XU7 SoC module depends on the
routing path for these signals. When using MGTs at high performance rates, ensure adequate signal
integrity over the full signal path.
NOTICE
Damage to the MGT transceivers
No AC coupling capacitors are placed on the Mercury+ XU7 SoC module on the
MGT transceivers.
GTH Transceivers
There are 16 GTH MGTs available on the Mercury+ XU7 SoC module organized in four FPGA banks ‐ Table
12 describes the connections.
The naming convention for the GTH MGT I/Os is:
MGT_B<BANK>_<FUNCTION>_<PACKAGE_PIN>_<POLARITY>.
For example, MGT_B228_TX2_M5_N is located on pin M5 of MGT I/O bank 228, it is a transmit pin and it
has negative polarity.
D‐0000‐443‐001
If required by your application, ensure that capacitors are mounted on the
base board, close to the module pins.
Value ﴾PL SYSMON﴿
1.8 V
Internal
0 ‐ 1 V
0.2 MSPS
16 ﴾only auxiliary inputs﴿
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