Display Port; Real-Time Clock ﴾Rtc; Usb 3.0 Implementation Example - Enclustra Mercury+ XU7 User Manual

A 100 MHz differential clock is available on the module and connected to PS_MGTREFCLK2 pins, to be
used as a reference clock for the USB 3.0 interface. It is also possible to provide another reference clock
from the base board to the MGTPS_REFCLK* pins.
Details on the built‐in USB 2.0/3.0 controller and on the usage of the PS GTR lanes are available in the
Zynq UltraScale+ MPSoC Technical Reference Manual [21] and in the Zynq UltraScale+ MPSoC Overview
[25].
Figure 11 shows an example of a USB 3.0 implementation using the built‐in AMD USB 3.0 interface and
the USB 2.0 signals from the PHY, all routed to a USB 3.0 connector on the base board.
Tip
The USB 3.0 interface on the Mercury+ XU7 SoC module uses the GTR signal lines ﴾MGTPS signals on
module connector B﴿, and not the USB_SSRX_P/N and USB_SSTX_P/N signal lines on module connec‐
tor A.
Figure 11: USB 3.0 Implementation Example
2.22

Display Port

AMD Zynq UltraScale+ devices feature two built‐in DisplayPort controllers and PHYs, supporting up to
two lanes at a 5.4 Gbit/s line rate. Each lane is represented by one of the PS GTR transceivers connected
to the module connector.
A 27 MHz differential clock is available on the module and connected to PS_MGTREFCLK3 pins, to be
used as a reference clock for the DisplayPort interface. It is also possible to provide another reference
clock from the base board to the MGTPS_REFCLK* pins.
Details on the built‐in DisplayPort controller and on the usage of the PS GTR lanes is available in the Zynq
UltraScale+ MPSoC Technical Reference Manual [21] and in the Zynq UltraScale+ MPSoC Overview [25].
2.23 Real‐Time Clock ﴾RTC﴿
Zynq UltraScale+ devices include an internal real‐time clock. The internal RTC can be accessed by the
platform management unit ﴾PMU﴿. More information on the PMU is available in the Zynq UltraScale+
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