Mdio Address; Phy Configuration; Rgmii Delays Configuration; Gigabit Ethernet Phys Configuration - Bootstraps - Enclustra Mercury+ XU7 User Manual

2.19.4

MDIO Address

The MDIO interface is shared between the two Gigabit Ethernet PHYs. These can be configured using the
corresponding address. The MDIO address assigned to PHY 0 is 3 and to PHY 1 is 7.
The MDIO signals are mapped to MIO pins 76 to 77 and they are routed directly to PHY 1 and via a level
shifter to PHY 0.
2.19.5

PHY Configuration

The configuration of the Ethernet PHYs is bootstrapped when the PHYs are released from reset. Make
sure all I/Os on the RGMII interface are initialized and all pull‐up or pull‐down resistors are disabled at
that moment.
The bootstrap options of the Ethernet PHYs are set as indicated in Table 30.
Strap Input Signal Value
MODE[3:0] 1110
011
PHYAD[2:0]
111
CLK125_EN 0
Table 30: Gigabit Ethernet PHYs Configuration ‐ Bootstraps
For the Ethernet PHY configuration via the MDIO interface, the MDC clock frequency must not exceed
2 MHz.
The PHY is configured in single LED mode with active‐low LEDs 1 and 2.
2.19.6

RGMII Delays Configuration

The two Ethernet PHYs are connected directly to hard MAC controllers present in the MPSoC device. In
order to achieve the best sampling eye for the RX and TX data, it is recommended to adjust the pad skew
delays as specified in Table 31. These values have been successfully tested on Enclustra side.
The delays can be adjusted by programming the RGMII pad skew registers of the Ethernet PHY. Refer to
the PHY datasheet for details.
D‐0000‐443‐001
Description
RGMII mode: advertise all capabilities ﴾10/100/1000, half/full duplex﴿
except 1000Base‐T half duplex.
PHY0: MDIO address 3
PHY1: MDIO address 7
125 MHz clock output disabled
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