Overview; Introduction; Prerequisites - Enclustra Mars ZX2 User Manual

1 Overview

1.1

Introduction

The Mars ZX2 SoC module reference design demonstrates a system using the Mars ZX2 SoC module in
combination with the Mars ST3 base board. It presents the basic configuration of the device and contains
a guided getting started tutorial.
A troubleshooting section is included at the end of the document, to help the user solve potential issues
related to board connectivity and/or system functionality.
Please note that the features presented in the reference design depend on the employed base board,
therefore some features may not be available in certain hardware configurations.
An introduction to the Xilinx tools is provided by the documents below:
Vivado Design Suite User Guide, Embedded Processor Hardware Design [1]
Zynq®7000 All Programmable SoC Embedded Design Tutorial [2]
More information on the Mars ZX2 SoC module and the Mars ST3 base board can be retrieved from their
respective user manuals [3] [4].
The following directory structure applies to the ZX2 Reference Design:
src
scripts
doc
Pre-generated binaries for any ZX2 variant are released on the ZX2 Reference Design Github page.
1.2

Prerequisites

IT
A computer with a microSD card slot (optional
Software
Xilinx Vivado 2022.1 WebPack, Evaluation, Design or System Edition (check the Mars ZX2 SoC
Module User Manual [3] for details on device support in Xilinx tools)
Xilinx Vitis IDE
Enclustra Module Configuration Tool (MCT) [5] (optional
A terminal emulation program (e.g. Tera Term)
Hardware
An Enclustra Mars ZX2 SoC module
An Enclustra Mars ST3 base board
Accessories
A 12 V DC power supply
A standard micro USB cable
A Xilinx JTAG programmer (e.g. Platform Cable USB II) (optional
1
Only required for SD card boot mode
2
May be used for flash programming, for SoC device configuration or for FTDI configuration.
3
Any FTDI device present on Enclustra hardware can be configured to Xilinx JTAG mode using the Enclustra MCT software [5].
D-0000-489-003
— Xilinx pinout and timing constraints and VHDL source code directory
— Scripts directory required for Vivado project creation
— Reference Design documentation
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) running Windows 10 64-bit (or later)
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)
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)
Version 2022.1_v2.0.1, 15.10.2022