Programmable Logic (Pl); Gpios; Xadc; Fpga Firmware I/O Configuration - Enclustra Mars ZX2 User Manual

2.2

Programmable Logic (PL)

2.2.1

GPIOs

A Xilinx GPIO controller in the PL is connected to the PS via an AXI bus. The PL GPIOs are connected to
LEDs in the top level, as described in Table 3.
The PL firmware contains a 24-bit counter freely running at 50 MHz. The MSB of this counter is used to
blink LED0#_PL with a frequency of approximately 3 Hz.
FPGA Pin Signal
R19 LED0#_PL
T19 LED1#_PL
G14 LED2#_PL
J15 LED3#_PL
Table 3: FPGA Firmware I/O Configuration
2.2.2

XADC

A Xilinx XADC IP core instance is connected to the PS via an AXI bus, in order to monitor the temperature
of the device. The temperature threshold for the FPGA is configured to its maximum allowed temperature.
The constraints provided in the reference design enable FPGA bitstream power-down, when the temper-
ature increases above the threshold. In this case, the PL will be reset, while the ARM processor will still
be running.
Depending on the user application, the Mars ZX2 SoC module may consume more power than can be
dissipated without additional cooling measures; always make sure the SoC is adequately cooled by in-
stalling a heat sink and/or providing air flow. Temperature control and monitoring is very important in a
complex design.
Information that may assist in selecting a suitable heat sink for the Mars ZX2 SoC module can be found
in the Enclustra Modules Heat Sink Application Note [10].
D-0000-489-003
Function
Blinking LED counter MSB
GPIO 1, controlled by the PL GPIO controller
GPIO 2, controlled by the PL GPIO controller
GPIO 3, controlled by the PL GPIO controller
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