Troubleshooting; Vivado Issues; Vitis Issues; Jtag Connection Issues - Enclustra Mars ZX2 User Manual

5 Troubleshooting

5.1

Vivado Issues

If the changes in the block design (including licenses for special IPs) are not propagated into im-
plementation, open the Hierarchy tab in Vivado and regenerate the block design files:
1. Right click on the block design file (.bd)
2. Click on Reset Output Products
3. Click on Generate Output Products
During block design generation Vivado reports a critical warning (CRITICAL WARNING: [PSU-1]
Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.026 . PS DDR inter-
faces might fail when entering negative DQS skew values.) which can be safely ignored for ZYNQ
7000 PS DDR interfaces. For more details please refer to this Xilinx forum post.
If programming fails with the error "Problem in running uboot" and "Flash programming initializa-
tion failed", the modified FSBL from chapter 4.1.2 can be used.
5.2

Vitis Issues

If the platform generation in Vitis is not successful or the generated platform is not selectable for
applications:
1. Close Vitis
2. Delete the workspace folder
3. Restart Vitis and try creating the platform again.
If Vitis shows the warning "There's no DDR_1 in the HW design. MMU translation table marks 32
GB DDR... " please check if more than 2GB PS DDR4 memory should be available. For detailed
information please check the Xilinx Answer Records and Forum about this warning.
5.3

JTAG Connection Issues

If the JTAG cable is not detected, the following steps should be followed:
1. Make sure that the hardware configuration is made according to Section 3.2
2. If built-in JTAG is used, check that the FTDI device is configured to Xilinx JTAG mode. This
can be done using the Enclustra MCT software [5]. More information on the Xilinx JTAG mode
configuration on the Mars ST3 base board can be retrieved from the Mars ST3 base board user
manual [4].
3. Check that only one JTAG adapter is active and connected to the hardware at a given moment.
Make sure that you are not using both built-in JTAG and Xilinx Platform Cable USB.
4. Remove the USB connection and the power supply from the Mars ST3 base board and close
Vitis
5. Reconnect the USB and power supply and start Vitis again
6. Check for UART Connection Issues (refer to Section 5.4)
7. Reboot the computer if the problem persists
If no device is detected, shutdown the hw_server process e.g. in the Windows Task Manager and
try again.
5.4

UART Connection Issues

If the computer is not able to recognize the USB UART on the Mars ST3 base board:
1. Check that the USB cable is connected properly
2. Check that the FTDI VCP drivers are installed
(a) Disconnect all JTAG connections
D-0000-489-003
Reset
Generate OK
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