Sd Card; I2C; Quad Spi Flash Controller; Uart - Enclustra Mars ZX2 User Manual

2.1.3

SD Card

The SD card is configured in the PS to the MIO 40..45 and 50 pins. This enables SD card access, as well
as booting from the SD card.
To allow the Mars ZX2 SoC module to boot from the SD card, the hardware configuration on the Mars
ST3 base board must be done according to Section 4.2.2.
Please note that the SD pins are shared between the PS and the PL.
Warning!
On the modules with XC7Z020 FPGA devices, some pins are shared between the PL and the PS. Because
the MIOs 40..45 & 50 are connected to FPGA pins W10, W9, W11, Y11, Y9, Y8 & T9 in parallel, make
sure the FPGA pins are in high impedance state before driving the PS SD pins and vice versa.
2.1.4

I2C

The I2C controller I2C0 is configured to the 14..15 pins. The I2C1 controller is configured to the EMIOs.
For available devices on the I2C bus refer to the Mars ZX2 SoC Module and Mars ST3 Base Board User
Manual [3] [4]. An I2C Application Note is available as well providing sample code and more details about
using I2C on Enclustra hardware [8].
Please note that the I2C pins are shared between the PS and the PL.
Warning!
On the modules with XC7Z020 FPGA devices, some pins are shared between the PL and the PS. Because
the MIOs 14..15 are connected to FPGA pins V8, W8 in parallel, make sure the FPGA pins are in high
impedance state before driving the PS I2C pins and vice versa.
2.1.5

Quad SPI Flash Controller

The quad SPI flash controller is connected to MIO 1..6 in Single Slave Select mode. MIO 2..6 pins are
shared between NAND flash and QSPI flash on the Mars ZX2 SoC module. Please refer to the Mars ZX2
SoC Module User Manual [3] for details about flash programming and usage.
To allow the Mars ZX2 SoC module to boot from the QSPI flash, the hardware configuration on the Mars
ST3 base board must be done according to Section 4.1.1.
2.1.6

UART

The UART0 is mapped to MIO 46..47 pins and connected to the FTDI controller on the Mars ST3 base
board. The UART is configured as shown in Table 2.
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