Reference Design Description; Processing System (Ps); Clocks; Ps Ddr3L Sdram - Enclustra Mars ZX2 User Manual

2 Reference Design Description

Enclustra Mars ST3 Base Board
Enclustra Mars ZX2 SoC Module
QSPI Flash
USB Host
USB PHY
Connector
Micro SD
Card Slot
RJ45 Ethernet
Connector PHY
Figure 1: Hardware Block Diagram
2.1

Processing System (PS)

2.1.1

Clocks

The PS input clock frequency is configured to 33.33 MHz, while the CPU clock is configured to its cor-
responding maximum CPU frequency. The maximum CPU clock performance depends on the device
speedgrade and package. Beside that a 50 MHz and a 100 MHz clock are exported from PS to the PL.
These clocks can be modified in the settings of the processing system in Vivado.
2.1.2

PS DDR3L SDRAM

The DDR3L SDRAM memory runs at its corresponding maximum PS DDR frequency at a voltage of 1.35
V by default. The clock frequency for the controller can be modified in the Zynq system.
The DDR settings in the Zynq system must be configured according to the Mars ZX2 SoC Module User
Manual [3].
D-0000-489-003
Xilinx Zynq-7000 SoC
Processing System (PS)
ARM Cortex-A9 CPU
QSPI
Controller
USB
Controller Controller
SDIO
Controller Controller
Ethernet SDRAM
MAC Controller
Programmable
Logic (PL)
XADC
5 / 25
UART
EEPROM
EEPROM
I2C 0
RTC
I2C 1
DDR3
SDRAM
GPIO LEDs
Version 2022.1_v2.0.1, 15.10.2022
Micro USB
Connector
FTDI
USB
Device
Controller
HDMI
Transceiver