Advantech PCIE-1751 User Manual page 29

Counter Input
The voltage logic level between the counter input (counter clock, counter gate,
counter arm, and sample clock) terminals and the digital ground (DGND) terminal is
measured. To prevent undetermined or fluctuating results when input is floating, the
counter input signals are internally pulled-up. This is shown in Figure 3.4
Figure 3.4 Counter input signal connection
Counter Output
A voltage logic level is generated between the counter output terminal and the digital
ground (DGND) terminal. This is shown in Figure 3.5.
Figure 3.5 Counter output signal connection
Each counter output channel can source or sink only a finite amount of current. If this
limit is exceeded, the output voltage will not stay at the specified voltage logic level.
Refer to the device specifications for the maximum source and skin current values.
21 PCIE-1751 User Manual