Advantech PCIE-1751 User Manual page 13

3. Pulse Width Measurement:
In pulse width measurement mode, both the high period and the low period of
the counter clock signal are measured. The measured values are updated when
a pulse is completed. This is shown in Figure 1.6.
Figure 1.6 Pulse width measurement
4. Timer/Pulse with Interrupt:
In timer/pulse mode, continuous pulses with specified frequency are generated
at the counter output terminal, and an interrupt is also generated with each
pulse as shown in Figure 1.7.
Figure 1.7 Pulse output and timer interrupt
The output can be gated. If the counter gate is at an active level, pulses are out-
put normally. On the other hand, if the counter gate is at an inactive level, output
is disabled. Figure 1.8 shows an example of an active high gate.
Figure 1.8 Gated timer/pulse output
5 PCIE-1751 User Manual