Advantech PCIE-1751 User Manual page 14

5. One-Shot (Delayed Pulse Generation):
In one-shot mode, when an active edge of gate signal is detected, a pulse will
be generated after the specified number of source clock counts. The pulse width
is one period of the source clock. Figure 1.9 shows an example of high-pulse, 5-
clock delay one-shot output.
6. Pulse Width Modulation Output (Finite/Infinite):
In pulse width modulation (PWM) output mode, a pulse waveform with specified
high period (tHIGH) and low period (tLOW) is output at the counter output termi-
nal as shown in Figure 1.10.
The number of pulses generated can be finite or infinite. For finite pulse genera-
tion, the counter output starts generating pulses when armed, and automatically
stops after the specified number of pulses has completed. The counter can be
re-armed after the previous generation is completed. This is shown in Figure
1.11.
PCIE-1751 User Manual
Figure 1.9 One-shot operation
Figure 1.10 Pulse width modulation output
Figure 1.11 Finite pulse generation
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