Clock Interface; Digital Audio Interface - Lexicon 960L Service Manual

CTLREG(4) RW
CTLREG(3) RW
CTLREG(2) RW
CTLREG(1) RW
CTLREG(0) RW

Clock Interface

The following onboard digital audio clocks are derived from bus clocks TMIX_CKI and TMIX_WCKI:
I2S_FS/, I2S_64FS/, and I2S_256FS The bus clocks TMIX_CKI/2, IOBUS_WCLK/, IOBUS_64FS/, and
IOBUS_256FS are not used. I2S_FS/ and I2S_64FS/ scale with sample rate FS. I2S_256FS is the master
clock to the D/A converters, and is zzzcheck this (make sure 2x operation is right – see AOUT design)
256FS in single-speed mode and 128FS in double-speed mode. Source resistors in the clock lines reduce
ringing due to reflections to provide proper clocking.

Digital Audio Interface

Audio data flows between the IO cards(e.g. Analog Input, Analog Output, AES) on the IO backplane and
TMIX chips located on DSP(e.g. reverb) cards on the NLX backplane, over high speed serial audio
channels called octals. TMIX chips define the octal format and timing. The bit rate of an octal is either
11.2896 Mbps for a 44.1Khz word clock or 12.288 Mbps for a 48Khz-word clock. An octal channel contains
eight time slots. Each time slot can carry a 24-bit sample with up to 8 bits of status per sample. Note that
the TMIX interface does not directly support double speed sampling rates.
Within U1, the four I2S stereo streams from the converters are merged into a pair of octal serial digital
audio channels (at 11.2896 or 12.288 Mbps) to feed A/D input into the system via the I/O backplane.
At double-speed sampling rates(88.2/96Khz), each octal carries 4 audio samples during each I2S word
clock period, so a pair can carry all 8 samples. Within a pair, samples from odd-numbered input channels
(lefts) are split off and carried by one member of the pair(TMIX1_SERD0/2/10), even-numbered ones
(rights) by the other(TMIX1_SERD1/3/11).
This division is the same at single-speed rates, and so is the bit rate, but fewer actual input samples are
being provided by the converters. After a group of 4 samples has been clocked out at high speed, the next
word clock has not occurred and there are not yet any new samples to follow. In this case, the FPGA
hardware repeats the previous group, so that in single-speed mode, there are two successive groups of 4
samples within each word clock period that are the same. In both single- and double-speed modes, two
high-speed channels are necessary to carry 8 samples.
U1 is capable of driving one of 3 alternate channel pairs, SDO0/1, SDO2/3, or SDO10/11, on the
backplane. System software loads the CTLREG register within U1 to enable the drivers for one of the
available pairs, driving 8 channels from one Analog Input card into the system.
Should only be set if the AKM5394 is used.
NA Reserved
0 DFS1 : AKM5394 DFS1 control signal. Setting is
only significant if AKM5394 AD is used.
0 DFS0. Double Speed Sampling Enable for AKM4393.
0 CONV_RESET. Active High. AD converter reset control line. All converters are
reset when asserted.
Software must assert, then negate CTLREG(1) to complete a soft reset sequence.
NA Reserved
Lexicon
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