Peripheral I/O Subsystems - Lexicon 960L Service Manual

960L Multi-Channel Digital Effects System Service Manual
Boot Flash memory occupies address space: 0x0000 0000 to 0x0001 FFFF.
Program Flash (U10, U13, U14, U16, sheet 2)
The program Flash uses the PCMCIA socket 0 interface. It can also be addressed through CS1 address
space. This will result in the possibility of having dual entries in the cache. Care should be taken when
updating this flash that all entries in the cache are invalidated before doing an update to this Flash. The
memory consists of four 16 MBit Flash memory chips. The memory is organized as 2 MBytes by 32 bits.
The flash is not byte-writeable and must be written on word boundaries (32 bits).
Program Flash memory occupies address space: 0x0800 0000 to 0x087F FFFF.

Peripheral I/O Subsystems

FPGA, U18 (sheet 3)
The FPGA connects to the cpu address and data buses to interface the cpu with peripheral subsystems. It
controls the fader motors, the fader position A/D converters, and the PS-2 keyboard port. Additionally, it
acts as a conduit for buffering other peripheral data to the cpu.
These functions are described in the following sections.
Keypad (sheet 8)
The keypad is a rubber assembly containing molded-in conductive pellets. When a key is pressed, its pellet
makes a connection between the two halves of a corresponding gold-plated finger pattern on the main pc
board. The patterns are organized for scanning as 5 rows by 8 columns. Under software control, the array
is scanned by setting one of the row drive lines (RD_KBD [4:0]) to a high level. Each driveline connects to
the switch matrix SROW [4:0] through a corresponding diode and resistor (D9-D13, R51-R55). If a keypad
switch connected to the driven row is pressed, it connects its row and column, forcing the corresponding bit
of the column byte SCOL[7:0] high. Un-driven column bits remain at a low level due to 1K pull-down
resistors. A read instruction issued by the CPU asserts the ENA_KBD/ strobe, enabling two 4-bit sections of
buffer U24 (74LVC16244) to drive the bidirectional 8-bit LB_D[7:0] bus of FPGA U18. U18 in turn places the
byte on the CPU data bus SA_D[7:0] where it is read by the software.
The diodes on the row drivelines prevent multiple simultaneous switch closures from short-circuiting the
RD_KBD outputs of U18. Note that in this scanning circuit, two simultaneous switch closures can always be
sensed properly; however, this is not true for every combination of 3 or more switch closures because two
closures on the same column unavoidably cross-connects two rows, with the result that the other switches
on those rows become indistinguishable.
The SA-1100 scans the keypad matrix using 5 address lines. Each address has 8 data bits and is one row
within the matrix. A bit that is set to 1 in the register indicates that the key is down.
7-44