Power On Diagnostics; Power On Diagnostics Sequence - Lexicon 960L Service Manual

960L Multi-Channel Digital Effects System Service Manual

POWER ON DIAGNOSTICS:

There are two LED's located on the LARC2 Main Board which are used for displaying the status of the
Power On Diagnostic tests that are performed before the LED's on the Meter Board or LCD display are
enabled. Upon normal power up, the two LED's 'MSB(1)' and 'LSB(0)' perform a binary countdown from 3 to
0 (11, 10, 01 & 00).
NOTE: There are no error messages during this portion of the Power On Diagnostics. In the event that a
diagnostic failure has occurred, the system will halt on the failed test. The binary value displayed on the two
LED's indicates where the failure occurred during the Power On Diagnostic test sequence.

Power On Diagnostics Sequence:

When the LARC2 is first powered on, all of the LED's on the Meter Board and Main Board (keypad) will be
turned on for approximately 5 seconds, during this period the following sequence of operations are
performed as the Power On Diagnostic tests are executed. These operations are all being executed from
the Boot ROM.
Initialization:
•
During this operation, the SA-1100 is reset, its registers are initialized, the interrupts are disabled, and
the Main Board LSB(0) and MSB(1) LED's are turned on to display the binary value of 3.
MSB(1) ON, LSB(0) ON:
Determine Boot Cause:
•
During this operation, the Boot cause is determined, which is normally because reset has been
detected.
Boot ROM Checksum:
•
During this operation, the checksum of the Boot ROM is verified, and the Main Board LSB(0) LED is
turned OFF to display the binary value of 2.
MSB(1) ON, LSB(0) OFF:
Memory Test (DRAM Data Bus):
•
During this operation, the DRAM Data Bus is tested by first writing 00000000 (hex) into 512 memory
locations of the DRAM, then the same 512 locations are read to verify the data written in these
locations is correct. The same write/read sequence is also performed using the following (hex) values:
FFFFFFFF, AAAAAAAA, 55555555, CCCCCCCC, 33333333, 99999999 & 66666666.
During the test, the DRAM data lines (SA_D0-SA_D31) are tested using the data patterns listed in the
table below. Refer to the table below for the hex to binary conversion of the data patterns: FFFFFFFF,
AAAAAAAA, 55555555, CCCCCCCC, 33333333, 99999999 & 66666666.
During the test, the DRAM data lines (SA_D0-SA_D31) are tested using the data patterns listed in the
table below. Refer to the table below for the hex to binary conversion of the data patterns:
M
HEX S
VALUE: B
00000000 0000 0000 0000 0000 0000 0000 0000 0000
6-26
BINARY CONVERSION:
L
S
B