Lexicon 960L Service Manual page 124

960L Multi-Channel Digital Effects System Service Manual
Motor Drivers (sheet 5)
The motors on the faders are driven using the raw +12 volts through SGS-Thompson Push-Pull drivers.
Software loads an eight word by 32-bit memory array within the FPGA with bit patterns that determine the
waveforms that are the inputs to each pair of drivers for each fader. The column of the array is scanned at a
programmable clock rate. At the beginning of each column clock the row clock cycles through each row and
with the enable bit and the direction bit latches the corresponding output registers to generate an individual
differential drive waveform for each motor, the MOTOR + and MOTOR – signals.
At the end of the 32 bit-shifts, the process starts again, forming a continuous train of drive pulses. It is the
responsibility of the software to stop the motors by either writing zeros in the enable register or by setting all
the memory waveform bits to zero. The MTR_ENAB GPIO bit is a master enable to all motor-driver chips.
From CPU
8 x 32 Bit Ram
Position Sensing (sheet 5)
Each motorized fader is based on a 10K linear sliding potentiometer. Each potentiometer is connected to a
dc source (5VA) and produces a 0-to-5V dc voltage proportional to its position. To digitize the position
information, each voltage is fed to one channel of A/D converter U30. The serial port of the converter is
scanned under the control of FPGA U18. U18 supplies the serial input to control the channel multiplexing
and receives the serial output from the resulting A/D conversions, converting the data from serial to parallel
and storing the results in a memory block within the FPGA itself. The saved position locations of the faders
are eight 10-bit registers located on word boundaries. These registers are cleared upon power-on or after a
software reset.
Motor Power (12V) Sensing (sheet 5)
Channel 2 of A/D U31 receives a voltage proportional to the main +12V, scaled by 1/3 by the voltage
divider formed by R120/R121. The voltage divider scales supply voltages from 0 to 15V to be within the 0-
5V range of the A/D.
Since LARC2 can be powered from the 960L or from the optional Power Pack, 12 volts can vary. This
provides software with a means to monitor the voltage for the motor drivers. The output waveform can then
be adjusted accordingly.
The 12V-sense register is cleared upon power-on or after a software reset.
Fader Nulling
Automatic nulling of a fader is based on a software feedback loop. When it is time to move the faders,
algorithms within the code calculate the difference between the desired target position and the current A/D
position data and issue appropriate control waveforms to the motors, factoring in the measurement of the
actual motor supply-voltage.
7-46
Dir
Reg
Mux
Enab
Reg
Figure 4-2 FPGA Internal Motor Control Logic
Motor
REG
+
Motor -
REG