Lexicon 960L Service Manual page 120

960L Multi-Channel Digital Effects System Service Manual
Read burst
Read burst
Write single
Write burst
Write burst
Write burst
Write burst
Refresh timing
The SA-1100 provides support for a CAS before RAS (CBR) refresh cycle which is shown below.
CPU CLOCK
MEM CLOCK
SA_CAS
SA_RAS
7-42
4 0 Generated by read buffer or DMA request.
4
8 0 Generated by cache line fills or read buffer
requests.
1 Any 1..4 bytes are written as specified by byte mask.
Generated by write buffer or DMA request.
2 0, 1, 2, All four bytes of each word are written.
4, 5, 6 Generated by write buffer or DMA request.
3 0, 1 All four bytes of each word are written.
4, 5 Generated by write buffer or DMA request.
4 0 All four bytes of each word are written.
4 Generated by write buffer or DMA request.
8 0 Cache line copyback. All 32 bytes are written.
Table 3-1 SA-1100 Transactions
Figure 3-1 Refresh Timing