Lexicon 960L Service Manual page 126

960L Multi-Channel Digital Effects System Service Manual
sampled 5000 times per second. The serial data is stored in parallel form in a memory block within the
FPGA, where software can read it via the FPGA parallel port as necessary.
PS/2 Keyboard Interface (sheet 7)
The PS/2 port (J19) allows the user to connect a PS/2 compatible keyboard to LARC2. Clock and
bidirectional data are driven by open-collector nand gate U1 (74ALS38) Logic within the FPGA receives
incoming serial data from the keyboard, checks the parity, and presents the data to the system as a byte of
data at address 0x1000 0700. The controller does not translate the scan codes. The controller also passes
command information serially with parity appended to the auxiliary device through address 0x1000 0700. A
read-only status register resides at 0x1000 0704.The PS/2 controller is a pass through interface and does
not support any of the controller commands.
Input and Output Registers
The output buffer is an 8-bit read-only register at address 0x1000 0700. When the output buffer is read, the
controller sends information to the SA-1100. The information can be keyboard scan codes or auxiliary
device data.
The input buffer is an 8-bit write-only register at address 0x1000 0700. When the input buffer is written to,
the input-buffer-full (bit 1) in the status byte is set to 1. The data is sent to the keyboard.
4.9.2. PS/2 Status Register
The PS/2 Status Register is an 8-bit read-only register at address 0x1000 0704.
4.9.3. Interrupts
The PS/2 Controller produces two interrupts TXRDY and RXRDY. TXRDY is connected to GPIO11 on the
SA-1100 and indicates that the input buffer is empty. This bit is set to 1 on power-on or reset. RXRDY is
connected to GPIO12 on the SA-1100 and indicates that that there is a byte in the output buffer. This is set
to 0 on power-on or reset.
LCD Interface (sheet 7)
The LCD interface that is on the LARC2 is a Passive Matrix Color Display with 640 x 240 dots.
This display is driven directly from the LCD interface native to the SA-1100 microprocessor. Encoded pixel
data is stored in the external DRAM and the LCD controller has its own dedicated DMA controller for
moving the data to the output FIFO. LCD contrast is adjustable by R136 (CONTRAST) located on the rear
panel. R136 is enabled by CONT_ON/ permanently asserted low. J1 and J3 support the pinouts of
alternative LCD modules.
Host Interface Port (sheet 7)
The Host Interface uses Serial Port 1 of the SA-1100. This port is a combination synchronous data link
controller (SDLC) and universal asynchronous receiver/transmitter (UART) serial controller. This port is
configured as a UART and is identical to Serial port 3. This connects to an ALS180 RS422 driver/receiver
(U2).
The pinout for the host interface is shown below.
7-48
Pin Description
1 Ground
2 ~RXD
3 TXD
4 Ground (SC)
5 Plus 12 Volts DC
6 Ground (RC)
7 RXD
8 ~TXD
9 Ground
Table 4-1 Host interface pinout